JPH01235337A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01235337A JPH01235337A JP6279888A JP6279888A JPH01235337A JP H01235337 A JPH01235337 A JP H01235337A JP 6279888 A JP6279888 A JP 6279888A JP 6279888 A JP6279888 A JP 6279888A JP H01235337 A JPH01235337 A JP H01235337A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- film
- gate oxide
- etching
- irregularity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 238000005530 etching Methods 0.000 claims abstract description 44
- 238000000034 method Methods 0.000 claims abstract description 28
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims abstract description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 11
- 239000011259 mixed solution Substances 0.000 claims abstract description 8
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims abstract description 6
- 239000000908 ammonium hydroxide Substances 0.000 claims abstract description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 abstract description 20
- 229910052751 metal Inorganic materials 0.000 abstract description 10
- 239000002184 metal Substances 0.000 abstract description 10
- 239000010410 layer Substances 0.000 abstract description 9
- 239000002344 surface layer Substances 0.000 abstract description 6
- 235000011114 ammonium hydroxide Nutrition 0.000 abstract 2
- 239000000126 substance Substances 0.000 abstract 2
- 230000015572 biosynthetic process Effects 0.000 description 11
- 230000003647 oxidation Effects 0.000 description 10
- 238000007254 oxidation reaction Methods 0.000 description 10
- 108091006146 Channels Proteins 0.000 description 8
- 239000000356 contaminant Substances 0.000 description 8
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 6
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 6
- 239000000243 solution Substances 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 238000009826 distribution Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 241000293849 Cordylanthus Species 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 241001553014 Myrsine salicina Species 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000009835 boiling Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 102220043690 rs1049562 Human genes 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Landscapes
- Weting (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
半導体装置の製造方法、特にウェーハプロセスにおける
酸化シリコン膜のウェットエツチング方法の改良に関し
、
基板面内における酸化シリコン膜のエツチングレートの
ばらつきをなくして素子特性のばらつきを抑え、歩留り
を向上させることを目的とし、水酸化アンモニウムと過
酸化水素と水の混液を用いて酸化シリコン膜のエツチン
グを行う工程を含んで構成する。[Detailed Description of the Invention] [Summary] Regarding the improvement of the wet etching method of a silicon oxide film in a semiconductor device manufacturing method, particularly in a wafer process, it is possible to improve device characteristics by eliminating variations in the etching rate of a silicon oxide film within the substrate surface. The method includes a step of etching a silicon oxide film using a mixed solution of ammonium hydroxide, hydrogen peroxide, and water in order to suppress variations and improve yield.
本発明は半導体装置の製造方法、特にウェーハプロセス
における酸化シリコン膜のウェットエツチング方法の改
良に関する。The present invention relates to a method for manufacturing a semiconductor device, and particularly to an improvement in a method for wet etching a silicon oxide film in a wafer process.
ＭＯ３型半導体装置のウェーハプロセス工程においては
、ゲート酸化膜のコントロールエツチング、或いは薄い
酸化シリコン膜の除去等に、ダメージ形成の少ないウェ
ットエツチング手段が用いられるが、極度に高集積化さ
れて、ゲート酸化膜の厚さが１０Å以下程度に極めて薄
く形成され、また素子領域幅も１μｍ以下のサブミクロ
ン幅に形成される超ＬＳＩ等においては、上記ウェット
エツチング処理におけるエツチング量のばらつきによっ
て、素子特性にばらつきを生じて歩留りが低下するとい
う問題があり、改善が要望されている。In the wafer process of MO3 type semiconductor devices, wet etching means with less damage formation is used for controlled etching of gate oxide films or removal of thin silicon oxide films, but with extremely high integration, gate oxide In VLSIs, etc., in which the film thickness is extremely thin (approximately 10 Å or less) and the device region width is submicron (1 μm or less), device characteristics may vary due to variations in the amount of etching in the wet etching process. There is a problem that this causes a decrease in yield, and an improvement is desired.
（従来の技術〕
ＭＯ３型半導体装置の製造工程においては、ゲート酸化
膜を形成した後、このゲート酸化膜を通してゲート酸化
膜下の基板面に闇値電圧調整用のチャネルドーズと称す
る不純物のイオン注入がなされるが、ｎチャネル素子と
ｎチャネル素子が併設されるＣＭＯ３半導体装置の製造
に際しては、例えばｎチャネル素子のチャネルドーズを
行う際にはｎチャネル素子のゲート酸化膜上をレジスト
膜で覆い、またｎチャネル素子のチャネルドーズを行う
際にはｎチャネル素子のゲート酸化膜上をレジスト膜で
覆って所望の素子領域に選択的に所望の不純物のイオン
注入がなされる。(Prior art) In the manufacturing process of MO3 type semiconductor devices, after forming a gate oxide film, impurity ions are implanted into the substrate surface under the gate oxide film through the gate oxide film, which is called a channel dose for dark voltage adjustment. However, when manufacturing a CMO3 semiconductor device in which an n-channel element and an n-channel element are installed together, for example, when performing channel dosing of the n-channel element, the gate oxide film of the n-channel element is covered with a resist film, Further, when performing channel dosing of an n-channel device, the gate oxide film of the n-channel device is covered with a resist film, and desired impurity ions are selectively implanted into desired device regions.
この際、レジスト膜で覆われたゲート酸化膜の深さ１０
μｍ以下程度の表層部にはレジスト膜からの金属汚染物
質の拡散による侵入があり、この金属汚染物質によって
ゲート酸化膜の耐圧が劣化するという問題がある。At this time, the depth of the gate oxide film covered with the resist film is 10
There is a problem in that metal contaminants diffuse into the surface layer of about μm or less from the resist film, and the breakdown voltage of the gate oxide film deteriorates due to these metal contaminants.
そこでゲート酸化膜の耐圧劣化を防止するために、上記
チャネルドーズを終わってレジスト膜を除去した後、コ
ントロールエツチング手段によりゲート酸化膜表層部の
金属汚染物質侵入領域の除去が行われる。Therefore, in order to prevent breakdown voltage deterioration of the gate oxide film, after the channel dose is completed and the resist film is removed, the region where metal contaminants have invaded the surface layer of the gate oxide film is removed by controlled etching means.
このコントロールエツチングは、従来は弗酸系のエツチ
ング液例えば１〜５％弗酸（）ＩＰ）溶液を用い、２０
〜３０人の程度の深さになされていた。Conventionally, this control etching uses a hydrofluoric acid-based etching solution, such as a 1 to 5% hydrofluoric acid (IP) solution, and
It was done to a depth of about 30 people.
またトランジスタの形成領域等を画定分離するフィール
ド酸化膜を選択酸化により形成した際、該選択酸化に用
いた耐酸化膜下部の薄い下敷き酸化膜をウォッシュアウ
トする際にも１〜５％ＨＦ溶液が用いられていた。Furthermore, when a field oxide film is formed by selective oxidation to define and separate transistor formation regions, a 1 to 5% HF solution is also used to wash out the thin underlying oxide film below the oxidation-resistant film used for the selective oxidation. It was used.
しかし上記ＨＦ溶液は３００人／分程度の比較的大きな
エツチングレートを有するために、基板面内において大
きなエツチングレートのばらつきを生ずる。However, since the above-mentioned HF solution has a relatively high etching rate of about 300 per minute, large variations in etching rate occur within the surface of the substrate.
第３図は５％）ＨＦ溶液で熱酸化による酸化シリコン（
ＳｉＯ□）膜を８０人エツチングした際の基板面内にお
けるエツチングレートのばらつきを示す図で、ｔａ＋は
エツチング液のＳｉＯ□膜厚の面内分布を示し、ｆｂ）
はエツチング後の５ｉ（ｈ膜厚の面内分布を示す。Figure 3 shows silicon oxide (5%) by thermal oxidation in HF solution.
This is a diagram showing the variation in etching rate within the substrate surface when a SiO□) film was etched by 80 people, where ta+ indicates the in-plane distribution of the SiO□ film thickness of the etching solution, fb)
indicates the in-plane distribution of 5i(h film thickness) after etching.
なお（Ｃ）は測定径路を示す。Note that (C) shows the measurement path.
そのため、前記ゲート酸化膜のコントロールエツチング
に際しては、基板面内においてゲート酸化膜厚に大きな
ばらつきを生じて、超ＬＳＩ等高集積化されて、ゲート
酸化膜厚が１００Å以下に設定される品種においては、
闇値電圧に大きなばらつきを生ずる。Therefore, when performing the controlled etching of the gate oxide film, there is a large variation in the gate oxide film thickness within the substrate surface, and in products that are highly integrated such as VLSI and the gate oxide film thickness is set to 100 Å or less, ,
This causes large variations in the dark value voltage.
また前記下敷き酸化膜のウォッシュアウトに際してはフ
ィールド酸化膜端部のバーズビーク部の後退量がばらつ
くので、ＩＬｓＩ等トランジスタ幅がサブミクロン幅に
設定される品種においては、トランジスタ幅の変動割合
が拡大してコンダクタンスが大きく変動する。Furthermore, when washing out the underlying oxide film, the amount of recession of the bird's beak at the edge of the field oxide film varies, so in products such as ILsI where the transistor width is set to submicron width, the rate of variation in transistor width increases. Conductance fluctuates greatly.
そしてこれらトランジスタ特性のばらつきによって歩留
りの低下を招（という問題があった。There was a problem in that the variation in these transistor characteristics led to a decrease in yield.
そこで本発明は、基板面内における酸化シリコン膜のエ
ツチングレートのばらつきをなくして素子特性のばらつ
きを抑え、歩留りを向上させることを目的とする。SUMMARY OF THE INVENTION Therefore, an object of the present invention is to eliminate variations in the etching rate of a silicon oxide film within the plane of a substrate, suppress variations in device characteristics, and improve yield.
上記課題は、水酸化アンモニウムと過酸化水素と水の混
液を用いて酸化シリコン膜のエツチングを行う工程を有
する本発明による半導体装置の製造方法によって解決さ
れる。The above-mentioned problems are solved by a method of manufacturing a semiconductor device according to the present invention, which includes a step of etching a silicon oxide film using a mixed solution of ammonium hydroxide, hydrogen peroxide, and water.
即ち本発明においては、水酸化アンモニウム（Ｎｉｌ、
０１１）と過酸化水素（１１２０□）と水（１１２０）
との混合液が、ＮＩ＋４０Ｈのエツチング作用によって
金属汚染物質をＳｉＯ□ごと除去すると同時に、１１□
０□の酸化作用によってエツチングレートの制御及び表
面荒れを防止する機能を有し、そのエツチングレートを
１〜５人／分程度に極め°Ｃ小さく抑えることができる
ことによって、基板面内のＳｉｎ、膜のエツチングレー
トのばらつきかきが第４図に示すように殆ど生じないと
いう実験結果に基づき、該ＮＨ，Ｏ１ｌと１１□０□と
ＨｚＯとの混液をＭＯ３型半導体装置の製造工程におけ
る金属汚染物質除去のためのゲート酸化膜の微小深さの
コントロールエツチングや、薄い酸化膜のウォノンユア
ウトに用いる。That is, in the present invention, ammonium hydroxide (Nil,
011), hydrogen peroxide (1120□) and water (1120)
The mixed solution with 11□ removes metal contaminants along with SiO□ by the etching action of NI+40H
It has the function of controlling the etching rate and preventing surface roughening by the oxidation action of 0□, and by keeping the etching rate extremely low to about 1 to 5 people/minute, it is possible to reduce the thickness of Si and films within the substrate surface. Based on the experimental results that there is almost no variation in the etching rate as shown in Figure 4, a mixed solution of NH, O1l, 11□0□ and HzO is used to remove metal contaminants in the manufacturing process of MO3 type semiconductor devices. It is used for micro-depth control etching of gate oxide films and for etching thin oxide films.
なお第４図において（ａ）はエツチング前のＳｉＯ□膜
厚の基板面内分布、（ｂｌはエツチング後の５ｉ０２膜
厚の基板面内分布を示す。In FIG. 4, (a) shows the in-plane distribution of the SiO□ film thickness before etching, and (bl) shows the in-plane distribution of the 5i02 film thickness after etching.
そしてこれによって、コントロールエツチング後のゲー
ト酸化膜厚の基板面内のばらつきや、オーバエツチング
による素子領域幅の変動等が防止されて素子特性が均一
化され、超ＬＳＩ等高集積化される半導体装置において
特に大きな歩留り向上が得られる。As a result, variations in gate oxide film thickness within the substrate surface after controlled etching and variations in device region width due to overetching are prevented, and device characteristics are made uniform, leading to highly integrated semiconductor devices such as VLSIs. A particularly large improvement in yield can be obtained.
以下本発明を、図を参照し実施例により具体的に説明す
る。Hereinafter, the present invention will be specifically explained by examples with reference to the drawings.
第１図は本発明の一実施例の工程断面図、第２図は本発
明の他の実施例の工程断面図である。FIG. 1 is a process sectional view of one embodiment of the present invention, and FIG. 2 is a process sectional view of another embodiment of the invention.
全図を通じ同一対象物は同一符合で示す。Identical objects are indicated by the same reference numerals throughout the figures.
第１図（ａ）参照
本発明の方法をゲート酸化膜のコントロールエツチング
に用いてＣＭＯ３半導体装置を製造するに際しては、通
常の方法で例えばｎ−型シリコン基板１に選択的にｐ−
型ウェル２が形成され、表面部に基板１面を表出する第
１の素子形成領域３＾とウェル２面を表出する第２の素
子形成領域３Ｂとを画定分離するフィールド酸化膜４及
びその下部のｎ型チャネルストッパ５及びｎ型チャネル
ストッパ６が形成されてなる従来同様の被処理基板を用
い、従来通り熱酸化手段により第１の素子形成領域３八
と第２の素子形成領域３Ｂの表面に厚さ例えば１００〜
１５０人程度のゲー程度化膜７八及び７Ｂを形成する。Refer to FIG. 1(a) When manufacturing a CMO3 semiconductor device by using the method of the present invention for controlled etching of a gate oxide film, for example, p-type silicon substrate 1 is selectively etched using a normal method.
A mold well 2 is formed, and a field oxide film 4 and a field oxide film 4 are formed on the surface portion to define and separate a first element formation region 3^ that exposes the first surface of the substrate and a second element formation region 3B that exposes the second surface of the well. Using a substrate to be processed similar to the conventional one on which the n-type channel stopper 5 and the n-type channel stopper 6 are formed, the first element forming region 38 and the second element forming region 3B are formed by thermal oxidation as in the conventional method. For example, the thickness on the surface is 100~
Formation layers 78 and 7B of approximately 150 people are formed.
第１図（ｂｌ参照
次いで従来同様の方法により該被処理基板上にチャネル
ドーズを行う例えば第１の素子形成領域３八面を表出す
る開孔８を有し、チャネルドーズを行わない第２の素子
形成領域３Ｂのゲート酸化膜７Ａ上を覆うレジスト膜９
を形成し、該レジスト膜９及びフィールド酸化膜４をマ
スクにし、ゲート酸化膜７Ａを通して、イオン注入手段
により第１の素子形成領域３Ａのｎ−型益板１面に１０
゛＋ｓ ｃｍ−”程度の燐Ｐ０のチャネルドーズを行う
。１１０はＰ゛ドーズ領域示す。FIG. 1 (see BL) Next, a channel dose is applied to the substrate to be processed by a method similar to the conventional method. A resist film 9 covering the gate oxide film 7A in the element formation region 3B of
is formed, and using the resist film 9 and field oxide film 4 as a mask, 100 nm is applied to one surface of the n-type gain plate in the first element forming region 3A by ion implantation through the gate oxide film 7A.
A channel dose of phosphorus P0 of approximately "+s cm-" is applied. Reference numeral 110 indicates a P dose region.
第１図（Ｃ）参照 次いで通常の方法で従来通りレジスト膜９を除去する。See Figure 1 (C) The resist film 9 is then removed in a conventional manner using a conventional method.
ここでレジスト膜９に覆われていたゲート酸化膜７Ｂ及
びフィールド酸化膜４の表層部には従来通りレジスト膜
９から拡散侵入した金属汚染物質含有層１１が形成され
る。Here, a metal contaminant-containing layer 11 is formed on the surface layer portions of the gate oxide film 7B and the field oxide film 4 that were covered with the resist film 9 by diffusing and penetrating from the resist film 9 as in the conventional method.
第１図Ｆｄｌ参照
次いで上記被処理基板を、６０〜８０℃程度に加温した
ＮＩ＋４０１１： １１，０□：ＩＩ□Ｏ＝１：１：４
の混液に浸漬し、ゲート酸化膜７Ａ、７Ｂ及びフィール
ド酸化膜４の表層部を２０人程度コントロールエ・ノチ
ングする。Refer to FIG. 1 Fdl. Next, the substrate to be processed was heated to about 60 to 80°C. NI+4011: 11,0□:II□O=1:1:4
About 20 people perform control etching on the surface layer parts of the gate oxide films 7A, 7B and the field oxide film 4.
このエツチングに要する時間は約４〜２０公人度である
。ここで前記金属汚染物質含有層を含む鎖線で図示する
１２の部分が除去されて、ゲート酸化膜７八、７Ｂは８
０〜１３０人程度の所程度厚さになる。またフィールド
酸化膜４も２０人程度薄くなる。The time required for this etching is about 4 to 20 degrees. Here, 12 portions shown by chain lines including the metal contaminant-containing layer are removed, and the gate oxide films 78, 7B are removed by 8.
The thickness will be about 0 to 130 people. Furthermore, the field oxide film 4 is also thinned by about 20 layers.
第１図（ｅ）参照
以後従来同様の方法によりゲート酸化膜７＾、７Ｂ上に
ポリＳｉ等のゲート電極１３Ａ 、 １３Ｂを形成し、
ゲート電極１３Ａをマスクにし選択イオン注入手段で素
子形成領域３Ａに選択的に硼素を注入し、次いでゲート
電極１３Ｂをマスクにし選択イオン注入手段で素子形成
領域３Ｂに選択的に砒素を注入し、次いで活性化熱処理
を行って素子形成領域３Ａにｐ゛型のソース領域１４及
びドレイン領域１５を、また素子形成領域３Ｂにｎ゛型
のソース領域１６及びドレイン領域１７を形成する。こ
の際前記チャネルドーズ領域１１０はｎ型チャネル層１
０となる。Referring to FIG. 1(e), gate electrodes 13A and 13B made of poly-Si or the like are formed on the gate oxide films 7^ and 7B by a method similar to the conventional method.
Using the gate electrode 13A as a mask, selective ion implantation means selectively implants boron into the element formation region 3A. Next, using the gate electrode 13B as a mask, selective ion implantation means selectively implants arsenic into the element formation region 3B. Activation heat treatment is performed to form a p' type source region 14 and drain region 15 in the element forming region 3A, and an n' type source region 16 and drain region 17 in the element forming region 3B. At this time, the channel dose region 110 is the n-type channel layer 1.
It becomes 0.
そして以後、図示しない絶縁膜の形成、配線形成等がな
され、本発明の方法を用いたＣＭＯ３半導体装置が完成
する。Thereafter, an insulating film (not shown), wiring, etc. are formed, and a CMO3 semiconductor device using the method of the present invention is completed.
なお本発明に係るコントロールエツチング方法において
は、８０人エツチングした際にも前記第４図に示される
ようにｉｔｔ面内のエツチングレートのばらつきは極め
てすくない。従って２０人程度の微小厚さエツチングを
行う該実施例において基板面内のエツチングレートのば
らつきは殆ど顕現化されず、従って該コントロールエツ
チングによるゲート酸化膜の厚さのばらつきは殆ど生ず
ることがない。In the controlled etching method according to the present invention, even when etching is performed by 80 people, as shown in FIG. 4, variations in the etching rate within the itt plane are extremely small. Therefore, in this embodiment, in which about 20 people perform etching to a minute thickness, variations in the etching rate within the plane of the substrate are hardly realized, and therefore, variations in the thickness of the gate oxide film due to the controlled etching hardly occur.
第２図１ａｌ参照
また選択酸化手段により素子形成領域を画定分離する際
に本発明の方法を適用する際には、例えばｎ−型シリコ
ン基板１０表面に従来通り熱酸化法により厚さ２００人
程程度下敷きＳｉｎｇ膜１８膜形８し、次いで該下敷き
Ｓｉｎｇ膜１８上に素子形成領域３の形状に対応する耐
酸化膜例えば窒化シリコン（Ｓｉ３Ｎ４）膜パターン１
９を形成し、次いで該ＳｉＪ。Refer to FIG. 2 1al. When applying the method of the present invention to define and separate element forming regions by selective oxidation means, for example, the surface of the n-type silicon substrate 10 is coated with a thickness of about 200 by conventional thermal oxidation. An underlay Sing film 18 is formed into a film shape 8, and then an oxidation-resistant film, for example, a silicon nitride (Si3N4) film pattern 1 corresponding to the shape of the element formation region 3 is formed on the underlay Sing film 18.
9 and then the SiJ.
膜パターン１９をマスクにしてイオン注入によりチャネ
ルストッパ用の燐（Ｐ”）を選択的に注入する。ここで
１０５はど注入領域を示す。Phosphorus (P") for a channel stopper is selectively implanted by ion implantation using the film pattern 19 as a mask. Here, 105 indicates an implantation region.
第２図（ｂｌ参照
次いで従来通り５ｉ３Ｎｎ膜パターン１９をマスクにし
て選択酸化を行い厚さ５０００人程度０フィールド酸化
膜４を形成する。このフィールド酸化膜４の端部には公
知の薄い酸化膜よりなるバーズビーク１０４が形成され
る。またこの際同時に前に注入されたＰ゛は活性化際分
布してｎ型チャネルストッパ５が形成される。Refer to FIG. 2 (bl) Next, selective oxidation is performed using the 5i3Nn film pattern 19 as a mask in the conventional manner to form a 0-field oxide film 4 with a thickness of about 5000 layers. A bird's beak 104 is formed.At the same time, the previously implanted P is distributed during activation to form an n-type channel stopper 5.
第２図（Ｃ１参照
次いで燐酸煮沸処理等によりＳｉ、Ｎ、膜パターン１９
を除去した後、６０〜８０℃程度に加温したＮ）Ｉ４０
Ｈ： ＩＩ□０□： Ｈ２０＝１ ： １ ： ４の混
液により下敷きＳ ｉ ＯｚＰＱ １８をエソヂング除
去する。FIG. 2 (see C1) Next, Si, N, film pattern 19 is removed by phosphoric acid boiling treatment, etc.
N)I40 heated to about 60 to 80°C after removing
H: II□0□: H20=1:1:4 underlayer S i OzPQ 18 is removed by etching.
上記混液の熱酸化Ｓｉｎ、膜１８に対するエツチングレ
ートは１〜５人／分程度の非常に遅いレートであるので
、該エツチング処理においてフィールド酸化膜４が強く
オーバエツチングされバーズビーク部１０４が広く除去
されて素子形成領域が太き（拡大することがなくなり、
素子幅のばらつきは減少する。Since the etching rate of the thermally oxidized Sin film 18 of the above-mentioned mixed solution is a very slow rate of about 1 to 5 per minute, the field oxide film 4 is strongly overetched in the etching process, and the bird's beak portion 104 is widely removed. The element formation area is thicker (no longer expands,
Variations in element width are reduced.
そして以後例えば前記実施例の工程により半導体装置が
形成される。Thereafter, a semiconductor device is formed by, for example, the steps of the above embodiment.
以上説明のように本発明によれば、コントロールエツチ
ング後のゲート酸化膜厚の基板面内のばらつきや、オー
バエツチングによる素子領域幅の変動等が防止されて素
子特性が均一化され、超しｓｒ等高集積化される半導体
装置において特に大きな歩留り向上が得られる。As described above, according to the present invention, variations in gate oxide film thickness within the substrate surface after controlled etching and variations in device region width due to overetching are prevented, device characteristics are made uniform, and SSR is improved. A particularly large improvement in yield can be obtained in semiconductor devices that are integrated at equal height.
第１図ｆａ）〜ｔｅｌは本発明の方法の一実施例の工程
断面図、
第２図ｆａ）〜（Ｃ１は本発明の方法の他の実施例の工
程断面図、
第３図は従来のエツチングレートの面内ばらつきを示す
図、
第４図は本発明の方法によるエツチングレートの面内ば
らつきを示す図
でなる。
図において、
１はｎ−型シリコン基板、
２はｐ−型ウェル、
３Ａ、３Ｂは素子形成領域、
４はフィールド酸化膜、
５はｎ型チャネルストッパ、
６はｐ型チャネルストッパ、
７＾、７Ｂはゲート酸化膜、
８は開孔、
９はレジスト膜、
１０はｎ型チャネル領域、
１１は金属汚染物質含有層、
１２はエツチング除去部、
１３Ａ 、１３Ｂはゲート電極、
１４はｐ゛゛ソース領域、
１５はｐ゛型トドレイン領域
１６はｎ゛゛ソース領域、
１７はｎ゛゛ドレイン領域
を示す。
ホ畠明の〃５恥−突箱例Ｏ工程訪め口
穿 １ 口 （千〇１）
本全Ｂ胎宏勧−戴鞄例のＬ哩断面目
早 １ 口 （そ［Ｆ］２）
率 ３ （支）
（Ｒ＞ （し、）
Ａ奮トＢ月θと５３粁に５工２．７ラーシブし一トロ値
り直■トつ、３Ｈ′ホす目早 ４ 口Fig. 1 fa) to tel are process sectional views of one embodiment of the method of the present invention, Fig. 2 fa) to (C1 are process sectional views of another embodiment of the method of the present invention, and Fig. 3 is a process sectional view of an embodiment of the method of the present invention. Figure 4 is a diagram showing in-plane variations in etching rate according to the method of the present invention. In the figure, 1 is an n-type silicon substrate, 2 is a p-type well, and 3A is a diagram showing in-plane variations in etching rate. , 3B is an element formation region, 4 is a field oxide film, 5 is an n-type channel stopper, 6 is a p-type channel stopper, 7^, 7B is a gate oxide film, 8 is an opening, 9 is a resist film, 10 is an n-type Channel region, 11 is a metal contaminant-containing layer, 12 is an etching removal part, 13A and 13B are gate electrodes, 14 is a p'' source region, 15 is a p'' type drain region 16 is an n'' source region, 17 is an n'' drain Indicates the area. Ho Hatake Akira's 〃5 Shame-Example O process visit opening 1 mouth (1,001) Honzen B womb promotion-Dai bag example L cross section 1 mouth (so[F ]2) Rate 3 (branch) (R> (shi,) A striving to B month θ and 53 months, 5 hours 2.7 rashib, 1 toro price straight ■ totsu, 3H' home quickly 4 mouths
Claims (1)
酸化シリコン膜のエッチングを行う工程を有することを
特徴とする半導体装置の製造方法。A method for manufacturing a semiconductor device, comprising the step of etching a silicon oxide film using a mixed solution of ammonium hydroxide, hydrogen peroxide, and water.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63062798A JP2663946B2 (en) | 1988-03-16 | 1988-03-16 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63062798A JP2663946B2 (en) | 1988-03-16 | 1988-03-16 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01235337A true JPH01235337A (en) | 1989-09-20 |
| JP2663946B2 JP2663946B2 (en) | 1997-10-15 |
Family
ID=13210728
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63062798A Expired - Fee Related JP2663946B2 (en) | 1988-03-16 | 1988-03-16 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2663946B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5413678A (en) * | 1993-05-14 | 1995-05-09 | Texas Instruments Incorporated | Heated SC1 solution for selective etching |
| KR100486210B1 (en) * | 1997-09-12 | 2005-06-16 | 삼성전자주식회사 | Cleaning method of trench isolation for improvement of trench profile |
| KR100624089B1 (en) * | 2005-07-12 | 2006-09-15 | 삼성전자주식회사 | Method of forming a pattern, method of manufacturing a multi gate oxide layer and flash memory cell using the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5342670A (en) * | 1976-09-30 | 1978-04-18 | Nec Corp | Coupling cave-type delay circuit |
-
1988
- 1988-03-16 JP JP63062798A patent/JP2663946B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5342670A (en) * | 1976-09-30 | 1978-04-18 | Nec Corp | Coupling cave-type delay circuit |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5413678A (en) * | 1993-05-14 | 1995-05-09 | Texas Instruments Incorporated | Heated SC1 solution for selective etching |
| KR100486210B1 (en) * | 1997-09-12 | 2005-06-16 | 삼성전자주식회사 | Cleaning method of trench isolation for improvement of trench profile |
| KR100624089B1 (en) * | 2005-07-12 | 2006-09-15 | 삼성전자주식회사 | Method of forming a pattern, method of manufacturing a multi gate oxide layer and flash memory cell using the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2663946B2 (en) | 1997-10-15 |
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