JPH03160728A - Manufacture of transistor - Google Patents

Abstract

PURPOSE:To make unnecessary the etching removing process for an unnecessary oxide film by forming a side wall spacer through injecting oxygen ions into the surface layer of the side part on at least drain side of a gate electrode and then heat treating it. CONSTITUTION:After a low concentration drain 7 and a low concentration source 8 are formed in the surface of a substrate 1, oxygen ions 9 are injected from above of the substrate 1. This injection is carried out from obliquely upper right and left toward respective side parts on the drain 7 and the source 8 side of a gate electrode 4a into the gate electrode 4a as the center, and the oxygen ions are injected into the whole surface layer including both side parts of the gate electrode 4a. Then, heat treatment is carried out for the whole substrate including the gate electrode 4a to change the oxygen ion injected part in the preceding process into a silicon oxide layer 10. At that time, initial volume of the gate electrode 4a expands somewhat due to oxidation, so that the distance (w) between the both side parts of the gate electrode 4a including oxidized part, and in particular, the oxide layer part 10a in the gate electrode side part on the drain side can be used as a side wall spacer. Thus, etching treatment is made unnecessary and high precision work can be avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a method for manufacturing a transistor, and more particularly, to a method for manufacturing a lightly doped drain (LDD) structure type transistor.

(Note) Conventional technology The LDD structure type transistor itself is described in, for example, "rVLsI Manufacturing Technology" 22, published by Nikkei BP, January 14, 1989.
It is already known as shown on pages 23 to 23,
In a method for manufacturing such a transistor, usually, after forming at least a low concentration drain by ion implantation using the gate electrode as a mask, a sidewall spacer is provided at least on the side of the gate electrode on the drain side, and the sidewall is The method includes a step of increasing the concentration of the drain to a high concentration by ion implantation using the gate electrode with a spacer as a mask, except for at least the end portion on the gate electrode side.

To form the sidewall spacer, conventionally, a silicon oxide film is deposited to a thickness of approximately 1000 nm over the entire surface of the semiconductor substrate, including the area around the gate electrode after forming the low concentration drain, by chemical vapor deposition (CVD). Then, by anisotropic etching such as reactive ion etching (RIE), the silicon oxide film is left on at least the side of the gate electrode on the drain side, and this is used as a sidewall spacer.

(c) Problems that the invention aims to solve: However, the etching when forming the sidewall spacer must be performed with high precision. I move on. Furthermore, in the case where the gate oxide film under the gate electrode is extended over the drain and ion implantation is performed through the extended oxide film when forming the drain, the gate oxide film under the gate electrode is extended over the drain. The sidewall spacer oxide film is also deposited on the
The process of etching away only the extended oxide film is also complicated.

Therefore, the present invention provides a novel manufacturing method that eliminates these drawbacks.

(2) Means for Solving the Problems In the method of the present invention, in manufacturing an LDDH4 transistor, the sidewall spacer is formed by implanting oxygen ions into the surface layer of at least the drain side of the gate electrode, and then It is characterized by being formed by heat treatment.

(E) Effect According to the present invention, a silicon oxide film is formed by oxygen ion implantation and heat treatment, and becomes a sidewall spacer.Therefore, unlike the conventional sidewall spacer type, unnecessary oxide film etching is not required. No removal step is required.

(f) Example FIGS. 1 to 7 show an example method of the present invention in the order of steps.

In the process shown in Figure 1, a thick silicon oxide film (2
) and a thin silicon oxide film (3) with a thickness of 300 mm are formed. The latter oxide film (3) has a gate oxide film portion (3a) located under the gate electrode formed in a later step,
The extended oxide film portion (3b) is separated from the extended oxide film portion (3b).

In the step shown in FIG. 2, a polycrystalline silicon film (4) with a thickness of 4,000 wafers is deposited on the entire surface of each oxide film (2) and (3) by low pressure CVD, and further, a polycrystalline silicon film (4) with a thickness of 4000 nm is deposited on the entire surface of each oxide film (2) and (3).
The patterned resist (5) is shaped. The polycrystalline silicon film (4) is given conductivity by adding P (phosphorus).

In the step shown in FIG. 3, the polycrystalline silicon film (4) is anisotropically etched by RIH, leaving the polycrystalline silicon film directly under the resist (5), which forms the gate electrode (
4a).

In the step shown in FIG. 4, the resist (5) from the previous step is removed, and then phosphorus ions (6) are implanted at a low concentration from above the substrate through the extended oxide film (3b).

At this time, the gate electrode (4a) serves as a mask, and a low concentration drain (7) and a low concentration source (8) are formed on the substrate surface. The ion implantation conditions are: ion species 11p, implantation energy 60 KeV, and dose IXIO''/cm2.

In the step shown in FIG. 5, oxygen ions (9) are implanted from above the substrate. The injection at this time is performed not diagonally above the left and right sides of the gate electrode (4a) in order to direct it to each side of the gate electrode (4a) on the drain (7) and source (8) sides. As a result, oxygen ions are implanted into the entire surface layer including both sides of the gate electrode (4a). The ion implantation conditions were as follows: ion type 0'' implantation energy 32KeV, dose amount I x 10''/cm'', and implantation depth approximately 500.

In the step shown in FIG. 6, the entire substrate including the gate electrode (4a) is subjected to heat treatment, thereby converting the oxygen ion implanted portion in the previous step into a silicon oxide layer (10). At this time, due to such oxidation, the volume of the original gate electrode (4a) expands slightly, and as a result, the gate electrode (4a) including the oxidized portion
The distance W between both sides is increased by about 1000 compared to the original value, and in particular, the oxide layer portion (10a) on the side of the gate electrode on the drain side is used as a sidewall spacer.

The heat treatment in this step is at 900°C in a nitrogen atmosphere.
, under heating conditions of 30 minutes. At this time, an annealing effect on the implanted ions shown in FIG. 4 also occurs.

In the step shown in FIG. 7, arsenic ions (11) are implanted from above the substrate through the extended oxide film (3b), and then a normal heat treatment is performed. At this time, the gate electrode (4a) with the oxide layer (Hl) serves as a mask, and the highly concentrated drain (
l2) and the source (13) are shaped.

Therefore, the low-concentration drain (7) and source (8) that have already been formed are in a high-concentration state, but due to the presence of the oxide layer portion (10a) that acts as a sidewall spacer, the high-concentration drain (7) and source (8) are in a high concentration state. The end portion (7a) on the gate electrode side of 12) remains with a low concentration, forming an LDD structure.

In this example, since there is an oxide layer on both sides of the gate electrode 1tM (4a), similarly, the gate electrode side end (8a) of the high-intensity source (13) also remains at a low concentration. It happens. The ion implantation conditions were ion species “As” and implantation energy 8.
0 KeV and a dose of 15×10”/cm′.

Thereafter, the transistor is completed through well-known processes such as source and drain contacts, wiring, passivation 3, etc.

In this embodiment, the silicon oxide layer (10) that grooves the sidewall spacer is provided on both sides of the gate electrode (4a), but it may be used at least only on the side on the drain side. .

Further, in this embodiment, ion implantation for high concentration source and drain operations was performed through the extended oxide film (3b), but such oxide film may be removed in advance. .

(g) Effects of the invention According to the invention, the LD using side wall spacers1)Ill
In the 91st method of modeling transistors, the ffll
``Due to the shape of the f-spacer, conventional etching is not required, thus freeing the user from the high precision work associated with conventional etching.Also, in place of the conventional etching process, the present invention This process includes ion implantation and a deep treatment process, and this process itself is simpler than the etching process.

Furthermore, normally, in the double-notching process of polycrystalline silicon gate electrodes, etching residues are likely to be generated in the high step portions, which causes leakage defects between wirings, but according to the present invention, the presence of such residues can be eliminated. However, that... There is no problem because silicon oxide is similarly formed by heat treatment with 1 ton of oxygen ions when forming the sidewall spacer.

4,

[Brief explanation of the drawing]

Figures 1 to 7 are An example method of the present invention will be described. FIG.

Claims (1)

[Claims] (1) After forming at least a low concentration drain by ion implantation using the gate electrode as a mask, a sidewall spacer is provided at least on the side of the gate electrode on the drain side, and the gate electrode with the sidewall spacer is used as a mask. In the method for manufacturing a transistor with a low concentration drain structure, which includes the step of making the drain highly doped by ion implantation except for at least an end on the gate electrode side, the sidewall spacer is arranged in the drain at least on the drain side of the gate electrode. 1. A method of manufacturing a transistor, characterized in that the transistor is formed by implanting oxygen ions into a side surface layer and then subjecting it to heat treatment.