JPH01222513A - Phase correction device - Google Patents

Abstract

PURPOSE:To make the phase of an output signal constant by varying a count initial value set to a counter so as to revise the phase difference at the time resetting the phase difference between an input signal and a signal outputted from the counter in the case of reset. CONSTITUTION:Reset circuits 15, 19 resetting counters 12, 17 in the initial state using the content of registers 16, 20 as the count initial value synchronously with the input signal are provided to the device. Then the phase of the signal outputted from the counters 12, 17 is deviated with respect to the input signal by the value corresponding to the count initial value. Since the phase difference between the input signal and the signal outputted from the counters 12, 17 depends on the count initial value of the counters 12, 17 set by resetting, that is, the content of the registers 16, 20, the phase difference is varied by revising the content of the registers 16, 20. Thus, the phase of the output signal is kept constant.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a phase correction device that converts an input signal of a constant frequency into a signal having a constant phase difference with respect to the input signal and outputs the signal.

BACKGROUND OF THE INVENTION FIG. 4 is a block diagram showing the configuration of a reference signal generating device provided in a conventional video printer. This reference generator is NTSC (National Te
1evision System II Com+m1tt
ee) input the horizontal synchronization signal and vertical synchronization signal separated from the video signal, and output a signal having a constant phase difference with respect to these horizontal synchronization signal and vertical synchronization signal. be. In the figure, 1 is a crystal oscillator with an oscillation frequency of 14, +3 MHz, and the next stage counts the pulses output from the crystal oscillator 1 and calculates the frequency 2 f - (1/455 of the pulses).
= 14, 3 MHz x 1/455).
counter 2 is connected. The next stage of the counter 2 has a frequency of 1/2 of the pulse that is output from this counter 2 and inputs it! H< = 1-'1
, 3 MHZ X l , / 455 X l , /
2 = 15.7kHz) is connected, and the next stage of the frequency divider 3 receives the above-mentioned pulses of frequency 2f8 and pulses of frequency f,
A horizontal synchronization decoder 4 is connected which outputs a horizontal synchronization pulse having a frequency f9 having a constant duty ratio (the ratio between the H section and the section of the pulse).

5 is a horizontal synchronizing signal EXT, H input from outside the device.
This is a horizontal synchronization reset circuit that receives the signal and provides the first counter 2 with a reset signal synchronized with this signal.

On the other hand, the next stage of the first counter 2 is the frequency divider 3 described above.
and a first counter 2 apart from the horizontal synchronization decoder 4.
115 of the pulses are counted.
25 frequency fv (=14°3 MHz x 1
/ 455 x 1 / 525 = 60 Hz >
A second counter 6 is connected which functions as a frequency divider and outputs a pulse having a value of . Further, connected to the next stage of the second counter 6 is a vertical synchronization decoder 7 that receives the above-described pulse of frequency f7 and outputs a vertical synchronization pulse of frequency fv having a constant duty ratio.

8 is a vertical synchronizing signal EXT, V input from outside the device.
This is a vertical synchronization reset circuit which receives the signal and provides the second counter 6 with a reset signal synchronized with this signal. 9 receives the horizontal synchronization pulse output from the horizontal synchronization decoder 4 and the vertical synchronization pulse output from the vertical synchronization decoder 7 as input signals, and outputs a composite synchronization pulse obtained by combining these signals in the form of a serial signal. This is a multiple synchronous decoder.

The operation of the reference signal generator described above is performed as follows.

The frequency output from the crystal oscillation ill is 14.3MHz
The pulse of is given a frequency of 2f-(-
31.4Hz), and this pulse is further converted to a frequency III (=15.7kHz) by frequency divider 3.
is converted into a pulse of This pulse is decoded by the horizontal synchronization decoder 4 into a pulse with a constant duty ratio,
It is extracted as a horizontal synchronizing pulse of frequency f (=15.7 kHz). Moreover, in the horizontal synchronization reset circuit 5,
Horizontal synchronization signal EXT supplied from outside the device.

I], and a reset signal synchronized with this signal is outputted.The first counter 2 receives this reset signal and is reset. That is, the count value of the first counter 2 is set to an initial value of 0 in synchronization with the start time of the horizontal synchronization signals EXT and H input from outside the device. Therefore, the phase of the horizontal synchronization pulse taken out from the horizontal synchronization decoder 4 based on the pulse output from the first counter 2 is determined by the horizontal synchronization signal EX input from the outside.
It is determined by the T and H phases.

Similarly, the frequency R2fs output from the first counter 2
The second counter 6, which converts the pulses of 1 to 60 Hz, is reset in response to a reset signal output from the vertical synchronization circuit 8. This reset signal is a signal synchronized with vertical synchronization signals EXT and V input from outside the device. therefore,
The count value of the second counter 6 is set to the initial value O in synchronization with the start point of the vertical synchronization signal EXT, V input from the outside of the device, and the count value of the second counter 6 is set to the initial value O, and the count value of the second counter 6 is set to the initial value O. The phase of the vertical synchronization pulse taken out from the vertical synchronization decoder 7 is matched with the phase of the vertical synchronization signal EXT, V input from outside the device. Also * ,
#The synchronization decoder 9 outputs a composite synchronization pulse in which a horizontal synchronization pulse and a vertical synchronization pulse are combined in the form of a serial signal. The horizontal sync pulse extracted in this way,
The vertical sync pulse and composite sync pulse are used as reference signals to control other mechanisms of the video printer.

Problems to be Solved by the Invention By the way, in the reference signal generating device described above, an input signal inputted from outside the device, for example, a horizontal synchronizing signal EXT
, H and the output signal output from the reference signal generator based on this signal, that is, the horizontal synchronizing pulse, is always constant (nearly 0 in the case of the above-described configuration). For this reason, for example, the horizontal synchronization signal separated from the video signal,
When one circuit is selected from a plurality of signal processing circuits with different delay times according to i%, and processing is performed such as passing it through that circuit, the horizontal synchronizing signal that has passed through that signal processing circuit is selected. The delay time will differ depending on the signal processing circuit used. Therefore, the phase difference between the signal before passing through the signal processing circuit and the output signal, ie, the horizontal synchronizing pulse, differs in intensity depending on the selection of each signal processing circuit described above, and the obtained horizontal synchronizing pulse is the standard. It becomes inappropriate as a signal.

Therefore, an object of the present invention is to provide an input signal that is input from the outside of the device after being delayed by an intermediate signal processing circuit,
It is an object of the present invention to provide a phase correction device capable of performing phase correction at any time for input signals whose delay times differ depending on the signal processing circuit so that the phase difference of an output signal becomes constant.

Means for Solving the Problems The present invention is a phase correction device that converts an input signal of a constant frequency into a signal having a constant phase difference with respect to the input signal and outputs the signal, the phase difference being larger than the input signal. an oscillator that generates clock pulses with a constant frequency; a counter that counts the clock pulses and outputs a signal with the same frequency as the input signal; and a register that can change and store data at any time; and the input signal. a reset circuit that resets the counter to an initial state in which the contents of the register are set as the initial counting value, and an amount corresponding to the initial counting value;
This is a phase correction device characterized in that the phase of a signal output from a counter is shifted with respect to the input signal.

Effect According to the present invention, the phase difference between the input signal and the signal output from the counter is determined by the initial counting value of the counter that is reset and set, that is, the contents of the register, so the contents of the register cannot be changed. The above phase difference can also be changed by

Embodiment FIG. 1 is a block diagram showing the configuration of an embodiment of the phase correction device of the present invention. The phase correction device of this embodiment is applied to a device that creates a reference signal used to control other mechanisms of a video printer based on a synchronization signal separated from a video signal based on the NTSC system. In FIG. 1, 11 is a crystal oscillator with an oscillation frequency of 14.3MH7. The next stage of this crystal oscillator 11 counts the pulses output from the crystal oscillator 11 and calculates a frequency 2 f of 1/455 of the pulses.
, l (= 14, 3 MHz × 1 / 455
) is connected to a first counter 12 which outputs a pulse having a value of . That is, this counter 12 has a function as a frequency divider. The pulse output from this counter 12 is input to the next stage of the counter 12, and the frequency is 1/2 of that pulse! , (=14, 3MHzxl/4
55X1/2=15. 313 is connected to output a pulse with a frequency of 7 kHz), and the next stage of the frequency divider 13 is connected to
A horizontal synchronization decoder 14 is connected to the horizontal synchronization decoder 14, which receives the pulses of frequency I and l and converts the pulses of frequency I and l into horizontal synchronization pulses of the same frequency f11 having a constant duty ratio. 15
is a horizontal synchronization reset circuit which receives horizontal synchronization signals EXT and H separated from the video signal and inputted from the outside of the phase correction device, and supplies a reset signal R not synchronized with this signal to the first counter 12. .

Reference numeral 16 denotes a first register that stores data that is set as an initial counting value in the first counter 12 when the first counter 12 is reset, in a rewritable manner at any time.

On the other hand, in the next stage of the first counter 12, in addition to the frequency divider 3 and the horizontal synchronization decoder 14 mentioned above, the pulses output from the first counter 12 are counted and the frequency of 11525 of the pulses is calculated. fv (=14, 3M H7
, X l , / 455 X 1 / 525 = 6
A second counter 17 is connected which outputs a pulse having a frequency of 0 Hz). That is, this counter 17 has a function as a frequency divider. At the next stage of the counter 17, a vertical synchronization decoder 18 receives the pulse of frequency fv output from the counter 17 and converts this pulse into a vertical synchronization pulse of the same frequency IV having a constant duty ratio.
is connected. 19 is a vertical synchronizing signal E that is separated from the signal 91 and input from outside the phase correction device.
A reset signal Rv that receives XT and V and is synchronized with this signal.
This is a vertical synchronization reset circuit that provides the second counter 17 with the following values. Reference numeral 20 denotes a second register that stores data that is given to the counter 17 as an initial count value when the second counter 17 is reset, in a rewritable manner at any time. Reference numeral 21 denotes a multiple synchronization pulse which receives the horizontal synchronization pulse outputted from the horizontal synchronization decoder 14 and the vertical synchronization pulse outputted from the vertical synchronization decoder 18 as input signals, and multiplexes these signals in the form of a serial signal. This is a multi-unit synchronous decoder that outputs .

FIG. 2 is a circuit diagram showing specific configurations of the horizontal synchronization reset circuit 15 and the vertical synchronization reset circuit 19. To explain the configuration of this circuit in the case of the horizontal synchronization reset circuit 15, in FIG. , the same pulse as the clock pulse input to the first counter 12 is inverted by the inverter 23 and provided. The next stage of the D flip-flop 22 is an output a from the non-inverting output terminal Q of the D flip-flop 22.
Another D flip-flop 24 is connected to the data input terminal D2, and the same pulse as the preceding D flip-flop 22 is applied to this D flip-flop 24 as a clock pulse. Further, in the next stage of the D flip-flop 24, the output from the inverting output terminal Q of this D flip-flop 24 and the output a from the non-inverting output terminal Q of the D flip-flop 22 in the previous stage are inputted. A NAND gate 25 is connected thereto. In the case of the vertical synchronization reset circuit 19, the input signals given to the data input terminals mentioned above are the vertical synchronization signals EXT,
V and the second counter 17 as a clock pulse.
The only difference from the horizontal synchronization reset circuit 15 is that the same pulse as that input to the horizontal synchronization reset circuit 15 is selected, and the overall configuration is exactly the same.

FIG. 4 is a timing chart 1 to illustrating the operation of the circuit of FIG. 3.

Next, the operation of the phase correction device described above will be explained.

The frequency output from the crystal oscillator 11 is 14°3M
Hz pulses are given a frequency of 2I by the first counter 12.
A (=31.4Hz) pulse, and this pulse is further divided by the frequency division 2513 into a frequency f l+(=
15,7 kHz) pulses. This pulse is processed by the horizontal synchronous decoder 14 at the same frequency J.
:! It is then decoded into a nodal synchronization pulse with a constant duty ratio and extracted.

In addition, in the horizontal synchronization reset circuit 15, D
The data input terminal of flip-flop 22 is connected to the third
Horizontal synchronization signal EXT with a waveform as shown in 1121(1)
, H are input, while the same pulse as the pulse input from the water crystal oscillator 11 to the first counter 12 is shown in FIG.
2) is input as a clock pulse with the waveform shown in FIG.
Provided to flops 22.24. A horizontal synchronizing signal EXT having the waveform shown in FIG. 3(1) is input to the data input terminal D1 of the D flip-flop 22.

H is held at the falling edge of the clock pulse as shown in FIG. Since the output from the non-inverting output terminal Q of the D flip-flop 22 in the previous stage is a is the third [m(3
), and the next stage D flip-flop 24
The output from the inverted output terminal Q has the waveform shown in FIG. 3 (4). Therefore, the output of the NAND gate 25 using these second outputs a and b as input signals, that is, the reset signal R1l output from the horizontal synchronous reset circuit 16, has the waveform shown in FIG. 3 (5) 9, that is, the reset signal R□ has almost the same starting point as the horizontal synchronizing signals EXT and H, and has a time width of one cycle of the clock pulse.

The first counter 12, which has been reset in response to the reset signal R1l, simultaneously reads the data previously stored in the first register 16 and sets this as the initial count value. Therefore, the first counter 12 counts the pulses subsequently output from the crystal oscillator 11 as follows:
We will start from the initial count value described above. For this reason,
The pulse output from the first counter 12 leads the horizontal synchronizing signal EXT, H in phase by an amount corresponding to the initial count value described above, and I! The horizontal synchronization pulses finally obtained also lead in phase.

On the other hand, the frequency 21. which is output from the first counter 12.
The pulse of
(=60Hz) pulse. This pulse is
The vertical synchronization decoder 18 converts the signal into a vertical synchronization pulse having the same frequency and a constant duty ratio and extracts it. As in the case of the horizontal synchronization reset circuit 15 described above, one vertical synchronization reset circuit receives the vertical synchronization signal EXT, V input from the outside of the phase correction device, and combines the vertical synchronization signal EXT, V with the signal. The starting point is almost the same and the frequency input to the second counter 17 is 2.7! A reset signal Rv having a time width corresponding to one cycle of the pulse , is output. The second counter 17, which has been reset in response to the reset signal Rν, simultaneously reads out the data previously stored in the second register 20, and sets this data as the initial count value. Therefore, the second counter 17 starts counting the pulses output from the first counter 12 from the above-mentioned initial count value. Therefore, the phase of the pulse output from the second counter 17 is advanced by an amount corresponding to the above-mentioned initial value of the count compared to the vertical synchronization signal EXT,V, and the vertical synchronization pulse finally obtained is also the same amount. The phase will advance. Note that the double synchronization decoder 21 outputs a multiple synchronization pulse in which a horizontal synchronization pulse and a vertical synchronization pulse are combined in the form of a serial signal.

In the above operation, for example, when the horizontal synchronization signals EXT and I-1 separated from the video signal are input to the horizontal synchronization reset circuit 15 after passing through an arbitrary signal processing circuit and being delayed by a certain period of time, the first register If you change the data stored in 1G to data corresponding to the above delay time,
The phase delay received by the horizontal synchronizing signal EXT, (■) in the signal processing circuit can be corrected when the first counter 12 is reset, and the phase of the horizontal coplanar pulse finally extracted can be adjusted to the phase before the delay. It can be made to match the phase of the horizontal synchronization signal. This also applies to the case where the vertical synchronization pulse is obtained from the vertical synchronization signals EXT and V.

In addition, while the horizontal and vertical synchronization signals separated from the video signal are input to the phase correction device without delay, the original video signal is then passed through a special signal processing circuit. When there is a delay, the above-mentioned PgJ is also used to adjust the phase of the delayed video signal and the horizontal synchronization pulse, vertical synchronization pulse, and composite synchronization pulse output as a reference signal from the phase correction device. Similar correction can be made by correcting the phase.

Effects of the Invention As described above, according to the phase correction 'A' of the present invention, the phase difference between the input signal and the signal output from the counter changes the initial counting value set in the counter at the time of resetting. Since the counter can be changed at any time, the phase of the signal output from the counter can always be kept constant even when the input signal is delayed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a phase correction device that is an embodiment of the present invention, FIG. 2 is a circuit diagram showing a different configuration of a horizontal synchronization reset circuit and a vertical synchronization reset circuit in the embodiment, and FIG. This figure is a timing chart showing the dynamic fF of the circuit shown in FIG. 2, and FIG. 4 is a block diagram showing the configuration of a conventional device. 11...Crystal oscillator, 12...1st color〉・Evening, 1
5...Horizontal synchronization reset circuit, 16...First register, 17...Second counter, 19...Vertical synchronization reset circuit, 20...Second register agent Patent attorney Nishikyo Keiichibe

Claims (1)

[Claims] In a phase correction device that converts an input signal of a constant frequency into a signal having a constant phase difference with respect to the input signal and outputs the signal, the device generates a clock pulse of a constant frequency higher than the input signal. a counter that counts the clock pulses and outputs a signal having the same frequency as the input signal; a register that can change and store data at any time; and a reset circuit for resetting the counter to an initial state in which the content is an initial counting value, and the counter is configured to perform a counter reset by an amount corresponding to the initial counting value.
A phase correction device characterized in that the phase of a signal output from a counter is shifted with respect to the input signal.