JPH01205359A - System for controlling input/output device - Google Patents

Abstract

PURPOSE:To enable the transfer of input/output information to from one and the same controller at a time without BUSY by storing the input/output information in a buffer memory, and taking and processing the stored input/output information asynchronously. CONSTITUTION:Respective boards 10 are provided with input/output buffer memories 15 to store temporarily the input/output information to be transferred between a host computer 2 and an input/output control part 1. Then, the storage and the processing of the input/output information are performed optionally at independent asynchronism by buffer control logical parts provided on the respective boards and the microprocessor 21 of an input/output control part 20. Thus, an input/output operation from the host 2 to the respective boards 10 can be performed simultaneously for every board 10, and besides, the host 2 comes free from wait or reject due to the BUSY of a device 1. Consequently, the use efficiency of a host interface 3 is improved, and BUSY reject processing at the host side is simplified.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a control system for computer input/output devices such as magnetic disk devices and magnetic tape devices, and particularly relates to control systems for computer input/output devices such as magnetic disk devices and magnetic tape devices, and in particular, for host interfaces, mutually independent and input/output control systems. The present invention relates to a control method for an input/output device suitable for adopting a configuration in which a plurality of four independent ports are waited for by a microprocessor in the unit.

[Conventional technology]

Conventionally, a control method that controls a common input/output device from multiple host computers via multiple ports, and the problem of input/output operation conflict between multiple ports in this control method, has been discussed, for example, with the IBM Systems/370 Architecture, by Barry Katzuan, Jr., translated by Makoto Inuhikata [Computer Organization and IBM Systems/370J (pp. 179-180), published by TBS in 1972. (Published by the Association). As stated in the above document, the common ports are designed to be selectively switched, so if a control device is in use via one port, processing via the other port is disabled. were either forced to wait or were busy and rejected.

[Problem to be solved by the invention]

In the above-mentioned conventional technology, no particular consideration is given to enabling simultaneous operation when input/output contention occurs between multiple ports on the same input/output control device.
If a host and an input/output control device are connected through a certain port and information is being transferred, if an attempt is made to connect to that input/output control device through another port or to transfer information,
The input/output control device is considered to be busy and is forced to wait or is rejected, resulting in a problem that the usage efficiency of the host interface decreases and rescheduling processing is required on the host side.

Therefore, an object of the present invention is to solve the above-mentioned problems of the prior art, and to enable each port to simultaneously operate independently of each other and independently of the control device without being busy, regardless of the state between other ports and the control device. An object of the present invention is to provide a control method for an input/output device that allows input/output information to be transferred to and from the same control device.

[Means to solve the problem]

In order to achieve the above object, the input/output device control method of the present invention is such that each host and the same person output control unit (including a microprocessor and its peripheral devices) control commands, etc. from the host at each of a plurality of ports. A buffer memory for temporarily storing input/output controller H information (commands and responses) transferred between the input/output device (controlling the input/output device according to the information) and a host for performing interface processing with the host. An interface control logic section and a port interface register for displaying the input state (storage state) of the hacker memory are provided. Also, provide a buffer memory manager in both the host interface control logic and the microprocessor. These buffer memory management units (for example, the buffer memory management unit on one of the host interface control logic units) check the input state of the buffer memory by referring to the port interface register, and perform the input to the buffer memory. Output control information (for example, commands) is stored, and (for example, the buffer memory management unit on the other microprocessor) asynchronously retrieves the stored input/output control information (the commands) at any time and performs the corresponding processing. be configured to do so.

[Effect]

The effect based on the above configuration will be explained.

The buffer memory and data transfer circuits on each port are independent of each other and enable simultaneous transfer of information between port hosts for information occurring simultaneously on multiple hosts or ports.

The port interface register is provided between each of the plurality of ports and the microprocessor, and each port interface register is assigned a pointer and a flag necessary for managing the buffer memory on the port, and Port and microprocessor status flags necessary for interface control are assigned.

Upon input of information from the host, the host interface control logic performs the following operations as a buffer management logic. That is, allocate an empty buffer according to the buffer management information on the port interface register (the various flags, pointers, address information, etc. of the allocated friends),
Control information (commands) is input (stored) by the data transfer circuit, and the input state is displayed on the port interface register. In addition, the buffer management cooking section of the microprocessor arbitrarily checks the port interface register at any time (asynchronously), and when input/output control information (command) is detected (stored), the corresponding input/output control information (command) is detected. Performs output processing, and sets the port interface register to release buffer No. 7 when the processing is completed. During this time, the next control information input is similarly input into the empty area of the buffer in parallel.

On the other hand, when outputting information (response, etc.) from the input/output control unit to the host through a certain port, the output information is created in a buffer free area determined from the buffer management information on the port interface register under the control of the microprocessor. Thereafter, when the host issues a request to output the current information to that port, the host interface control logic section outputs the information from the buffer management information on the port interface register to the data transfer circuit at any time (asynchronously) without microprocessor intervention. is sent, and the free status of the area on the sender is displayed in the port interface register. During this time, in parallel, the microprocessor may also create other output information in the buffer.

As a result of the above operation, the valley port on the input/output control information (input/output side ornament and port) is input to 'E7'C, 'C', 'C' and 'C', independently from other ports, regardless of the state of the microprocessor. Since the output is tiJ enabled, the host waits for access to the input/output control device, fcv is busy, and is rejected, so there is no interaction.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

FIG. 1 is a block diagram showing the configuration of an input/output control method according to an embodiment of the present invention, and the system includes a host computer 2. Consists of input/output device power [1] and input/output device power such as magnetic disk devices and magnetic tape devices. The input/output control device 1 includes a plurality of ports 10 corresponding to each host computer 2, and a device control section (device control section) that controls the input/output device [50]. The port 10 performs interface processing (hereinafter abbreviated as "I/F") with the host 2 via an interface circuit 14 connected to the host 2 via the host interface 3 and a protocol control processing bus 61, etc. A host E/F control cooking section 11 that executes;
A human output buffer memory 15 that stores input/output control information such as command information issued by the host 2 and response information from a device controller, and a port that displays and manages the input status of the human output buffer memory 15. ) An I/F register 13, a transfer control 63 for transferring the input/output control information to the input/output buffer memory 15, and a data transfer circuit 12. The device control unit is MPU (microprocessor unit))20. and a device control circuit 40 as its peripheral circuit. A data buffer (9) for storing input/output data for the input/output device output, a device data transfer circuit n for controlling data transfer between the input/output device output and the data buffer addition, a control bus for the device control circuit 40, and transfer control. It has a bus 72. The input/output buffer 15 has a stack management address table 100,
Command buffer 1 that stores commands from host 2
01 and a response buffer 101 for storing responses from the device control unit.

IP of this implementation ability! fe, the input/output buffer 15 is provided to temporarily store input/output control information such as commands and responses, and the port I/F register 13 stores the input status of this input/output buffer 150. This is the ninth item to display, configure, and manage. The host) I/F control logic section 11 and the microprocessor 21 of each port are provided with independent buffer management control sections. The buffer management units arbitrarily and independently manage the buffer input states of the input/output buffers 15 through the port E/F registers 13. Since this is K,
Input/output processing on the host 2 side relative to the port 10 and input/output processing on the device control unit side relative to the port 10 can be performed asynchronously with respect to each other.

Next, the operation of this embodiment will be explained in detail.

The host 2 issues commands via the host interface 3 connected to the input/output device power 10 which controls the input/output device power 10. The command issued is interface times M14 on the port,
Protocol control processing 6 using host I/F control logic 11
1, the data transfer circuit 12 and the transfer control, the command buffer 101 in the traffic buffer 15 on the port
will be stacked.

The input buffer area is determined from the stack management address table 100 and the contents of the port E/F register 13 by the access Φ path 62, and this command input work is performed without intervention from the microprocessor 21. The command input state should be set in the port I/F register 13. The microprocessor 21 accesses the port I/F register 13 at any time via the access bus 70, detects the input of a command from its contents, reads and decodes the command from the command buffer 101, and sends the command to the specified input/output device blade. Access is activated by the control path 71 and the device control circuit 40.

If there is input/output data for input/output device f5o, the data is transferred to bus 73? : Once added to the data buffer, the data is buffered. Data transfer between the data buffer and the input/output device is performed by the device data transfer circuit n and the 70 bus 72. Data transfer between the data buffer and the host 2 is performed by the host I/F control unit 11 on the port and the data transfer circuit 12 based on the buffer address and transfer ready information set in the port E/F register 13. . A response reported to the host 2 from the device control unit including command processing completion information is generated and stacked in the response buffer 102 on the port by the microprocessor 21. This stack area is the same as in the case of stone cloak, stack management address table 1
00, which is set by the microprocessor 21 and determined by the contents of the I/F register 13. The stacked response is sent to the host by the host I/F control logic 11 and the data transfer circuit 12 in response to the host's request, and the stack management address table 100 and the board I/F address table 100 are sent without the intervention of the microprocessor 21. F register 1
Start from the contents of 3.

Referring now to FIG. 2, the buffer memory management logic will be explained. In FIG. 2, 100 is a stack management address table on the input/output buffer 15, and 131 to 134 are port I
/F This is an instruction pointer on the register 13.

First, the case of command input will be explained.

On the stack management address table 100, each address of n stack areas of the command stack is set in advance. When a command input instruction is received from the host 2, the host) I/F control logic unit 11 controls the port I/F control logic unit 11.
Command input card Pi existing on register 13,
131. The data transfer circuit 12 is instructed to the address of the command stack area 9 pointed to by the address of the command stack area 9, and a command is input.

After input, the pointer P1 is advanced to point to the next stack area AIO. On the other hand, the microprocessor is processing the input command processing pointers P2, 132 . The position of the input pointer P1 is compared with the position of the input pointer P1, and the command included in the difference between the positions of both pointers is arbitrarily taken out and processed as a stacked unprocessed command. In order to release the command stack of processing end information, the pointer P2 is advanced and history is read. Here, it is conceivable that the order in which the stacks are released is different from the order in which they are stacked, in which case the stack release pointers P3, 133.
may be stored in the port I/F register 13, the stack area address when the stack is released is registered at the position indicated by P3, and then P3 is advanced and updated. In either case, input pointers P1 to P21 or P31
If you set fc, LJ 1 to n, 1.2...
The stack area of the area included in P31 after passing through is
This means that it is open for command input, and P2 to P
When P3 is set, commands between P3 and P2 are being processed, and from P2 to P1, processing is started. In addition, the stack size is 134 to circulate and use the stack area.
It is possible to use the buffer cyclically by comparing each pointer P1 to P3 with the maximum value at the time of the new history, and if n is exceeded, the pointer is moved to the beginning. If Pl retreats to P2 (or P3 to P3 for convenience), the stack becomes full, but it must report its status to the host or change the stack size (number of stacks) of the mouse to suit the input and processing performance. ), the problem is resolved and there is no problem in the normal state of 2a.

Next, the case where a response is sent from the control device 1 to the host 2 will be explained. In FIG. 2, Pl is the response input pointer of the microprocessor 21, and P2 is the host I
/F If the response transfer pointer of the control logic unit 11 is used, control can be easily realized by the same operation as when inputting a command.

Here, since the input/output buffer 15 is accessed by each of the host I/F control section 11, data transfer circuit 12, and microprocessor 21, access conflict resolution means are required, but the data transfer circuit 12 is controlled by protocol control. RAM method (the buffer itself has two ports and the one with the earliest input takes priority) or By giving priority to the port side and using the fcA stop method, it is possible to implement the host IZF system without making the host IZF system wait. According to this implementation f91.1, each port can independently stack multiple commands from the host, can stack multiple responses from the 'gfc, control device, and is independent of the status of other ports. Hosts can arbitrarily transfer commands and responses to each other asynchronously without any intervention. Therefore, simultaneous transfer of control information or simultaneous transfer of control information and data information is also possible using the mantissa port.

In this embodiment, unlike the buffer 15, only one data buffer is provided, so data cannot be transferred between multiple ports at the same time. However, the data buffer is divided into multiple units and transferred to input/output ports. By dynamically allocating (by making each buffer area variable), input data is actually the same as the command stack means in the example, and output data is the same as the response stack means, by using management logic, you can easily transfer data information simultaneously. It can be realized.

〔Effect of the invention〕

As described in detail above, according to the input/output control method of the present invention, a buffer memory for temporarily storing input/output control information transferred between the host and the input/output controller is stored in each port, and each port The input control information is arbitrarily stored and processed independently and asynchronously by the buffer management logic section provided in the microprocessor of the I/O port, so that input from the host to each port of the I/O control device is Output operations can be performed simultaneously between each port, and the host is less likely to wait for requests due to a busy input/output control device, resulting in improved host interface usage efficiency and simplified busy reject processing on the host side. It has excellent effects such as

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a control system for an input/output device according to an embodiment of the present invention, and FIG. 2 is an explanatory diagram of buffer memory management logic. 1... Input/output ft1lJ 1141 device, 2.
...Host computer, 3...Host interface, 10...Port, 11...
...Host interface control logic section, 12...
...Data transfer circuit, 13...Port interface register, 14...Interface circuit, 15...° Song input/output parts 7 Amemo! j, 2o...
...I/O equipment & (device) control section #21...
・Microprocessor, 22...device data transfer circuit, 30...data buffer, 50...
...Input/output device (input/output device), 100...
・・・Stack management address table, 101・Song・
Command buffer, 102/song/response buffer. 131... Input pointer, 132...
Processing pointer. 133...Stack release pointer, 134...
...Stack size. 1st place, 2nd ward, Kuchi Eco-11! 34

Claims (1)

[Claims] 1. An input/output device having a plurality of host connection ports, an input/output device, and an input/output control unit that includes a microprocessor and its peripheral devices and controls the input/output device according to control information from the host via the port. In the control method, a buffer memory is provided on each of the ports and temporarily stores input/output control information transferred between the host and the input/output control unit, and a buffer memory is provided on each of the ports and is provided between the host and the input/output control unit. a host interface control logic unit for executing interface processing of the host interface, a port interface register on each port for displaying the input status of the buffer memory, and a host interface control logic unit for the host interface control logic unit and the microprocessor, respectively; and checking the input state of the buffer memory via the port interface register, storing the input/output control information in the buffer memory, and asynchronously retrieving the stored input/output control information and processing the input/output control information. 1. A control method for an input/output device, comprising: a buffer memory management section for controlling an input/output device.