JPH03156551A - Dma controller - Google Patents

Abstract

PURPOSE:To efficiently utilize plural channels by allocating an input/output equipment requiring DMA transfer to the arbitrary idle channel according to a control signal to be sent out from a CPU. CONSTITUTION:A CPU 5 detects the idle channel based on the state of a status register 12 and when the necessity of DMA transfer is generated, the control signal to designate the idle channel is outputted to a DMA controller 15. The gate of the register 12 is opened/closed according to a gate control signal to be supplied from an address decoder 14. An address to designate the channel is supplied to the decoder 14 as well similarly to an address decoder 13 and according to this address, the gate control signal is supplied. When the gate control signal to be inputted from the decoder 14 to the register 12 is 'L', the contents of a control register 11 are fetched into the register 12. When an access from the CPU 5 shows reading, this gate control signal is turned to be 'H' and the gate of the register 12 is opened. Then, data latched at the register 11 are inputted to the CPU 5.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a DMA controller device,
In particular, if multiple input/output devices such as computer peripheral storage devices such as magnetic disk devices and magnetic tape devices, or display devices that request DMA transfer are connected to the computer, a transfer waiting state occurs in this input/output device. The present invention relates to a DMA controller device for efficiently performing DMA transfer by reducing the number of transfers or wait state time.

(Prior Art) When it is necessary to transfer data at high speed between a computer memory and the input/output device, data is often transferred by DMA transfer without going through a CPU.

FIG. 3 is a block diagram showing the configuration of a conventional control device for DMA transfer, that is, a computer having a DMA controller.

In the figure, a DMA controller 15 is a control device for DMA transfer of data between the memory 9 and a plurality of input/output devices 20, 21, 22, 23 requesting DMA transfer.

The input/output devices 20 to 22 include input/output control units 20a, 2
DMA via 1a, 22a: l Citrola 15 DM
The input/output device 23 is connected to the A channel (hereinafter simply referred to as channel) 1, and the input/output device 23 is connected to the channel 2 via the input/output control section 23a. In this prior art example, channel 3.4 is idle.

A plurality of the channels 1 to 4 can be activated simultaneously.

The DMA controller 15 includes an interface 6 for connecting the CPU 5, a memory control unit 7 for controlling the memory 9, and priority control for channels 1 to 4.
It has a DMA control unit 8 for managing MA requests.

In the conventional device with the above configuration, when the need for DMA transfer arises, the CPU 5 outputs the input/output command signal S1 to the DMA controller 15, and the necessary channel is selected from channels 1 to 4 according to this signal S1. Ru.

In addition, in response to the signal S2, the input/output control units 2°a to 23
Among a, input/output devices S20 to 2 that require DMA transfer
The input/output control section connected to 3 is set to the input/output enable state.

Then, the input/output control units 20a to 23a as well as the input/output devices 2
The input/output command is transferred to the input/output devices 0 to 23, and in response, a DMA request signal is output from the input/output devices 20 to 23. This DMA request signal is sent to the DMA via channel 1 or 2.
It is manually operated by the control section 8. The DMA request signal further includes DM
The data is sent from the A control unit 8 to the CPU 5 via the interface 6. CPU5 that received the DMA request signal DREQ
sends an acknowledge signal DAC to the DMA controller 15.
Return K.

This acknowledge signal DACK is sent from the DMA control unit 8 to the input/output control units 20a to 23 via channel 1 or 2.
a and the input/output devices 20 to 23. The input/output devices 20 to 23 that have received the acknowledge signal DACK start transferring data to and from the memory 9.

The designation of addresses on the memory 9 for reading and writing data and the amount of data to be transferred are set in the memory control unit 7, and data is transferred between the memory 9 and the input/output devices 20 to 23 according to this setting data. will be held.

When the scheduled data transfer is completed, DM to CPU5 is sent.
The A request signal DREQ is cleared, and the acknowledge signal DACK is also cleared.

(Problems to be Solved by the Invention) The above-described conventional technology had the following problems.

For example, when channel 1 is used to transfer data between the input/output device 22 connected to channel 1 and the memory 9, other input/output devices 20 or If there are 21 DMA requests,
The DMA transfer of the input/output device 20 or 21 is in a waiting state until the data transfer between the input/output device 22 and the memory 9 is completed.

In other words, since the input/output devices 20 to 23 are hardware-connected to the scheduled channel, they are connected to the other channels 2 to 23 in terms of hardware.
Even if channel 4 is vacant, input/output devices 20 and 21 cannot transfer data to and from memory 9 using channels 2 to 4, and are in a waiting state.

In this way, in conventional devices, each input/output device is hardware-connected to one channel, making it inflexible, so even though it has multiple channels, it is difficult to use these channels. There was a problem with low efficiency.

SUMMARY OF THE INVENTION An object of the present invention is to provide a DMA controller device that can solve the above problems and increase the calculation speed of a computer by efficiently using a plurality of channels.

(Means and effects for solving the problems) The present invention solves the above problems and achieves the objectives by freeing input/output devices requesting DMA transfer in accordance with control signals output from the CPU. It is characterized in that it is equipped with channel relocation means for allocating channels to existing channels.

In the present invention having the above configuration, the input/output device and the channel are not connected by hardware, but by cpt
According to the control signal sent from t, input/output devices can be connected to vacant channels. Therefore, the input/output device does not wait for human output of data even though the channel is vacant.

(Example) The present invention will be described in detail below with reference to the drawings. 1st
The figure is a block diagram showing one embodiment of the present invention. In this figure, the same reference numerals as in FIG. 3 indicate the same or equivalent parts.

In the figure, input/output devices 20 to 23 are connected to channels 1 to 4 via a channel relocation circuit (channel relocatable circuit) 10.

The channel relocation circuit 10 is configured to allocate the input/output devices 20 to 23 to an empty channel among the channels 1 to 4 according to a control signal output from the CPU 5.

A specific circuit example of the channel relocation circuit 10 is shown in FIG. This figure shows a circuit that determines the input/output devices assigned to channel 1, and the circuits that determine the input/output devices assigned to channels 2 to 4 are configured similarly to this circuit.

In the figure, the control register 11 is composed of a latch circuit, and a control signal dO-64 outputted from the CPU 5 is latched in accordance with a latch signal supplied from the address decoder 13.

The latched signals dO to d4 are input to the decoder 16, and the outputs of the decoder 16 are the gates 20b to 23b.
is supplied to Gate 20 according to the output of decoder 16
b to 23b is opened, and input/output devices 20 to 23
is assigned to channel 1. Then, a DMA request signal DREQ and an acknowledge signal DACK are exchanged between the assigned input/output device and channel 1.

When the signal d4 is “L”, all gates 20b to
23b is closed and channel 1 is isolated from external input/output equipment.

An address specifying a channel is supplied to the address decoder 13, and a latch signal is supplied to a control register for each channel assignment (control registers for channels 2 to 4 are not shown) in accordance with this address. The latch signal is output when access from the CPU 5 is for writing.

The state of the control register 11, that is, the state of which input/output device is assigned to channel l, can be recognized by the CPU 5 via the status register 12.

Therefore, the CPU 5 detects an empty channel based on the state of the status register 12, and outputs a control signal to the DMA controller 15 to designate this empty channel when DMA transfer is necessary.

The gate of status register 12 is address decoder 1
It is opened and closed by the gate control signal supplied from 4.

This address decoder 14 also includes the address decoder 1.
3, an address specifying the channel is supplied,
According to this address, a gate control signal is supplied to a status register provided for each channel (status registers for channels 2 to 4 are not shown).

When the gate control signal input from the address decoder 14 to the status register 12 is "L", the contents of the control register 11 are taken into the status register 12. When the access from the CPU 5 is for reading, this gate control signal becomes "H" and the status register 12
gate is opened, and the data latched in the control register 11 is manually input to the CPU 5.

As described above, according to this embodiment, input/output devices can be assigned to arbitrary channels according to the control signal supplied from the CPU 5 to the channel relocation circuit 10.

Note that this embodiment shows an example in which four input/output devices are connected. The present invention is not limited to this, and the input/output devices are five.
When more than five devices are connected, the present invention can be carried out by changing the configuration of the decoder 16 so that five or more connected input/output devices are determined according to the values of the signals dO to d4.

(Effects of the Invention) As is clear from the above description, according to the present invention, it is possible to allocate an input/output device that requires DMA transfer to any vacant channel, so that reading data from the input/output device and It is possible to reduce the waiting state when storing data in input/output devices. As a result, a plurality of channels can be used efficiently and the calculation speed of the computer can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram of a channel relocation circuit, and FIG. 3 is a block diagram showing a conventional technique.

Claims (1)

[Claims] (1) CP data transfer between memory and multiple input/output devices
A DMA controller device that controls DMA without going through a U, including a plurality of DMA channels arranged between the memory and a plurality of input/output devices and capable of operating independently of each other, and requesting DMA transfer. A DMA controller device comprising: a channel relocation circuit that allocates an unused DMA channel among the plurality of DMA channels to an input/output device.