JPS61206066A - System for setting memory address - Google Patents

Abstract

PURPOSE:To set freely an optional area matching to the using condition of a shared memory by a system CPU by providing an address latch means to store the address of the shared memory and providing the common area at the shared memory. CONSTITUTION:An address latch circuit 22 is provided with a local CPU 2, and stores the address of the shared memory 3. Between systems CPU 1 and CPU 2, the common memory areas are set which both can read/write the data in the memory 3. Namely, first, the CPU 1 divides the head address of the area in the memory 3 through a common bus 4 into the lower order position and the higher order position and latches it to the circuit 22. Next, through a microprocessor 21 of the CPU 2 and an AND circuit 23, the area is determined, thereby the CPU 1 divides optimally the whole of the area of the memory 3 to areas on the processing and can be used. Consequently, the CPU 1 can freely set the common area matching to the using condition of the memory 3.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a memory address setting method, and particularly to a micro9 computer application system having a system CPU, a local CPU and a shared memory, and a local CPU.
This invention relates to a memory address setting method suitable for freely changing the memory access area of a shared memory performed by a PU.

BACKGROUND ART A conventional high-performance microcomputer application system, as shown in FIG. 2, has a system CPU 1 . The configuration is such that a local CPU 2 that performs individual processing such as input/output, and a shared memory 3 used by both CPUIs 2 and 2 are connected through a common bus 4. Note that the common bus 4 consists of an address bus, a data bus, and a control bus.

In the above system configuration, data transfer between the system CPUI and the local CPU 2 is performed by, for example, the local CPU
2 transfers data read from a floppy disk storage device (not shown) to a shared memory 3, and the system CPUI transfers the transferred data from the shared memory 3 to an internal memory (not shown).

However, the memory area of the shared memory 3 that can be commonly read/written by the system CPUI and the local CPU 2 is set within all addresses 0000H-FFFFH of the shared memory 3, for example, as shown in FIG. 3(a). from 1
000H-I FFF.

Since the memory area 3a in between is fixedly determined in advance, even if the system CPU wants to use the memory area 3a for another purpose, it cannot be easily changed.

As another example, as shown in FIG. 3(b), a memory area 3b that can be read/written similarly to the above.
(address C00OH-CFFFH) to the local CPU
2, the system CPU 1 accesses the specific address 0400H of the shared memory 3.

0401) (, respectively, set the lower value (00) and upper value (CO) of the start address COOOH of the above memory area 3b, the local CPU 2 reads them, and specifies that the area after that start address is the memory area 3b. Therefore, although it is more flexible than the above, it cannot be easily changed even when the system CPU wants to use the area of a specific address for another purpose.

Purpose The purpose of the present invention is to solve such conventional problems and to enable both the system CPU and the local CPU to read data in a microcomputer application system that has a system CPU, a local CPU, and a shared memory. /To provide a memory address setting method that allows a system CPU to freely set an arbitrary area according to the usage status of the shared memory using a simple and inexpensive method when determining a common area of a shared memory that can be written to. There is a particular thing.

Configuration In order to achieve the above object, the present invention has a system CPU
, a microcomputer application system having a local CPU and a memory section, an address latch means for storing the address of the memory section, and a common area in the memory section that can be read/written by both the CPUs of the section; The system CPU sets the start address of the common area in the address latch means, and the local CPU reads the start address and performs read/write operations on the common area.

Hereinafter, a detailed explanation will be given based on one embodiment of the present invention.

FIG. 1 is a circuit block diagram showing an embodiment of memory address setting according to the present invention. The system configuration of this embodiment is the same as that shown in FIG. 2 described above.

In the figure, 21 is a microprocessor that is a one-chip central processing unit of the local CPU 2, 22 is an address latch circuit that stores the address of the shared memory 3, and 23 is an address latch circuit that stores the address of the shared memory 3.
are AND circuits, and these are mounted on the local CPU 2 board.

In system CPU1 and local CPU2rrR,
When agreeing on a common memory area in the shared memory 3 where both parties can read/write data, the system CPU 1 must first be connected via the common bus 4 to a memory area similar to the one shown in FIG. ;, the first address 0000H of the memory area 3b is set to the lower value (00) and the upper value (CO
) and latched into the address latch circuit 22. Note that the data is latched by the address latch circuit 22.
I10 light (IOW) to the strobe (STB) terminal of
This is done by sending out a signal.

Next, the microprocessor 21 of the local CPU 2 outputs a negative read (RD) signal and a negative chip select (CS) signal to the AND circuit 23, and after the AND circuit logically ANDs them, the address latch circuit 22 Output·
By sending a negative signal to the enable (OE) terminal, the lower value (OO) and upper value (CO) that have already been stored can be
) and read the start address CO00 of memory area 3b.
Confirm M.

A data read or write operation to the memory area 3b is started.

The above-described common memory area 3b arrangement operation is performed at system startup (IPL) or every time a read/write command is sent.

In this way, by indicating and reporting the start address of the common memory area negotiated between the system CPUI and the local CPU 2 to the address latch circuit 22, the aforementioned specific address (0400H, 04
01H), and the system CPUI can use the entire area of the shared memory 3 by dividing it into areas optimally for processing purposes.

Effects As explained above, according to the present invention, the system CPU
Since the address latch circuit indicates and negotiates the start address of the common area of the shared memory where both the system CPU and the local CPU can commonly read/write data, the system CPU can use the shared memory without using any special hardware. Common areas can be arbitrarily arranged according to the situation.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram showing an embodiment of memory address setting according to the present invention, and FIG. 2 is a block diagram of the configuration of a microcomputer application system. FIGS. 3(a) and 3(b) are diagrams for explaining a method of determining a common memory area in a shared memory in a conventional example. 1 system CPU, 2: local CPU, 3: shared memory, 3a, 3b: common memory area, 3-ri, 3-2:
Specific address, 4: common bus, 21: microprocessor, 22 near address latch circuit, 23: AND circuit. Figure 1 Figure 2 Figure 3 (a)

Claims (1)

[Claims] (1) In a microcomputer application system having a system CPU, a local CPU, and a memory section, there is an address latch means for storing the address of the memory section, and a common feature that allows both CPUs to read/write data in the memory section. A memory address characterized in that an area is provided, the system CPU sets a start address of the common area in the address latch means, and the local CPU reads the start address and performs a read/write operation with respect to the common area. Setting method.