JPH0119785B2 - - Google Patents

Info

Publication number
JPH0119785B2
JPH0119785B2 JP21341182A JP21341182A JPH0119785B2 JP H0119785 B2 JPH0119785 B2 JP H0119785B2 JP 21341182 A JP21341182 A JP 21341182A JP 21341182 A JP21341182 A JP 21341182A JP H0119785 B2 JPH0119785 B2 JP H0119785B2
Authority
JP
Japan
Prior art keywords
logic
signal
output
binary signal
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP21341182A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59104846A (ja
Inventor
Kuniharu Hirose
Masayuki Oohama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP21341182A priority Critical patent/JPS59104846A/ja
Publication of JPS59104846A publication Critical patent/JPS59104846A/ja
Publication of JPH0119785B2 publication Critical patent/JPH0119785B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4906—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes
    • H04L25/4908—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes using mBnB codes
    • H04L25/491—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes using mBnB codes using 1B2B codes
    • H04L25/4912—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes using mBnB codes using 1B2B codes using CMI or 2-HDB-3 code

Landscapes

  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)
JP21341182A 1982-12-07 1982-12-07 Ｃｍｉ符号変換回路 Granted JPS59104846A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21341182A JPS59104846A (ja) 1982-12-07 1982-12-07 Ｃｍｉ符号変換回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21341182A JPS59104846A (ja) 1982-12-07 1982-12-07 Ｃｍｉ符号変換回路

Publications (2)

Publication Number Publication Date
JPS59104846A JPS59104846A (ja) 1984-06-16
JPH0119785B2 true JPH0119785B2 (enrdf_load_stackoverflow) 1989-04-13

Family

ID=16638780

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21341182A Granted JPS59104846A (ja) 1982-12-07 1982-12-07 Ｃｍｉ符号変換回路

Country Status (1)

Country Link
JP (1) JPS59104846A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6411421A (en) * 1987-07-03 1989-01-17 Fujitsu Ltd Code converting circuit

Also Published As

Publication number Publication date
JPS59104846A (ja) 1984-06-16

Similar Documents

Publication Publication Date Title
JPH03237832A (ja) データ・クロックのタイミング合わせ回路
JPH0119785B2 (enrdf_load_stackoverflow)
JPH0630491B2 (ja) デイジタル同期回路
EP0942533A2 (en) Circuit for Synchronisation
JPH1168861A (ja) 同時双方向送受信方法および同時双方向送受信回路
JPS59140559A (ja) バツフアレジスタ
KR100314675B1 (ko) 디지털 텔레비전의 양위상 디코더
JP3088433B2 (ja) Ｍｓｋ復調装置
JP2776642B2 (ja) チャタリング除去回路
JPS6314540B2 (enrdf_load_stackoverflow)
JP2827517B2 (ja) 位相同期回路
JPH0558299B2 (enrdf_load_stackoverflow)
JPH0193227A (ja) シグナリング挿入回路
JPH03236619A (ja) 高速用ディジタルフィルタ
KR900015450A (ko) 디지털 위상 동기회로
JPH01309447A (ja) 単線同期式通信方式
JPS61131655A (ja) サ−ビス符号插入制御方式
JPH04349720A (ja) Ａ／ｄ変換器
JPH0787379B2 (ja) Ｃｍｉ符号変換回路
JP2000068800A (ja) ヒゲ防止方式及び回路
WO1994011952A1 (en) Pseudo clock extractor
JPS57207461A (en) Demodulation circuit for digital data
JPS61128653A (ja) ディジタル情報受信再生装置
JPS6352809B2 (enrdf_load_stackoverflow)
JPS6240834A (ja) 符号伝送方式