JPH01188975A - High-speed data transfer system for multi-processor - Google Patents

Abstract

PURPOSE:To increase a data transfer speed by putting the memories used as I/Os between plural processors and a bus line and transmitting again the data received from the processors directly to the bus line after transferring these data to those memories via the serial bit signals as necessary. CONSTITUTION:In case the data are transferred to a processor MP1 from a processor MPn, the data to be transferred from the MPn are inputted to a memory MEMn used as an I/O additional to the MPn and then sent directly to a bus line BUS after said transfer is through. In the same way, the data can also be transferred to other terminal equipments from processors via the BUS like the transfer of data performed between processors.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a high-speed data transfer method in a multiprocessor converter system including a plurality of processors. 2. Description of the Related Art Techniques are being researched to improve processing speed by performing parallel and distributed processing on a series of programs using a multiprocessor computer system equipped with a plurality of serial bit compatible microprocessors each having a communication channel.

A typical example of a conventional multiprocessor computer system is shown in FIG.
Mx, M2, . The BU8 is connected to other control devices (not shown) such as a printer, CRT display, etc. via an input/output memory I/O. In a multi-processor computer system with such a configuration, when data is transferred from each processor to another terminal device via the bus line BtJS, all processors at the final end connected directly to the bus line via the adjacent processors are transferred. Uke and handover will be carried out sequentially until Tsusa.

The bus line B (J
It is necessary to transfer it to S.

However, in data transfer performed via adjacent processors in this way, each processor determines whether the received data is for itself or not, and also transfers data for other processors to the other adjacent processor. Not only does this increase the burden on each processor, resulting in a decrease in processing speed, but it also has the drawback that when the number of processors passing through increases, the data transfer rate drops significantly.

(Object of the Invention) The present invention has been made in order to eliminate the above-mentioned defects in data transfer in the conventional multiprocessor computer system, and by reducing the burden Z on other processors, the system The purpose of this invention is to provide a high-speed data transfer method in a multiprocessor that improves the processing speed of the entire system and the data transfer rate.

(Summary of the invention) In order to achieve this object, in the present invention, an I/O memory is inserted between each of a plurality of processors and a bus line, and data from the processors is transferred to the memory as a serial bit signal as needed. Then, the data is transferred directly to the bus line, or the data on the bus line is transferred to the memory and then transferred again to the processor.

(Example) The present invention will be described in detail below based on the illustrated example.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In the figure, MPI to MPn are processor units each having three communication channels, and these are connected in series through each other's communication channels, and the remaining communication channels of each processor and the bus line are connected to each other in series. I/O memo IJME 1 to MEMn'?
: Insert and connect.

Further, the processor unit located at the end of the processor, for example MP1, and the bus line BUS are directly connected as in the conventional example shown in FIG.

Further, other terminal devices (not shown) are connected to the bus line BUS via Ilo.

As a processor equipped with three or more communication channels, for example, a transputer (four communication channels) is commercially available, and the present invention can be implemented by using these.

According to the multi-processor combiner system configured as described above, data can be directly transferred to the bus line BtlS via the I/O memory IJMEMI to MEMn added to each as necessary, or the data can be transferred to the bus line BtlS. You can receive data directly from.

For example, if we consider the case of transferring data from processor MPn to MPl, the data to be transferred from MPn is input to the attached I/O memory MB M n, and after the transfer is completed, it is sent directly to the bus line BtJS. .

Such data transfer is limited to only between processors, but data transfer from the processor to other terminal devices via the bus line BUSff: can also be performed in the same way.

(Effects of the Invention) Since the present invention is configured and functions as explained above, data transfer between processors or between a processor and other terminal devices in a multiprocessor computer system can be extremely fast. can be done, and furthermore,
It is effective in reducing the burden on other processors during data transfer and improving the overall processing speed of the computer.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional multiprocessor computer system. MP! 〜MPn...山...processor. MEM, MBM l- to MEMn...
・I/O memory, BUS・・・・・・・
...bus line. Patent applicant: Toyo Tsushinki Co., Ltd. Figure 1

Claims (1)

[Claims] In a computer system in which only a specific processor among a plurality of processors connected to each other via a communication channel is connected to a bus channel, processors other than the specific processor are connected to the bus channel via an I/O memory. A high-speed data transfer method in a multiprocessor, characterized in that the plurality of processors can independently communicate with other processors or with other devices connected to a bus line by directly connecting them.