JPH04235660A - Common memory device and communication control method for multiprocessor system - Google Patents

Abstract

PURPOSE:To attain the effective transfer of date despite the increase/decrease of data quantity in a multiprocessor system by performing simultaneously the communication tasks through plural processor groups. CONSTITUTION:The optional one of processors 1-1-1-n sends the designated information on the partner processor of communication and the address and the word number of the transfer data on a memory circuit 8 to a communication control circuit 12 via the processor interface circuits 4-1-4-n. The circuit 12 transmits the interruption requests to each of designated partner processors of communication. Then each partner processor reads the designated transferred data out of the circuit 8 based on the designated information and via a memory access control circuit 6.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a common memory device and communication control method for a multiprocessor system.

0002

2. Description of the Related Art An example of a common memory device in a conventional multiprocessor system is shown in FIG. 1-1 to 1-n
is a processor, 2-1 is a system bus used for communication between each processor, 2-2 is a bus master that controls communication between processors on the system bus, and 3-1 to 3-n are common buses that allow processors to access a common memory device. It is a memory access bus. 4-1 to 4-n are processor interface circuits that communicate one-on-one with the processors 1-1 to 1-n, respectively, and 5-1 to 5-n are processor interface circuits 4-1 to 4-n and memory access circuits. A memory access bus that performs memory access between the control circuits 6, 6 is a processor interface circuit 4-1 to 4-
A memory access control circuit arbitrates memory access from n and performs memory access to the memory circuit 8; 7 is a memory bus through which the memory access control circuit 6 accesses the memory circuit 8; 8 is a memory circuit.

In the above configuration, the system bus 2-1
For example, two processors 1-1 and 1-2 transmit and receive data, or one processor 1-1 performs broadcast communication such as transmitting data to other processors 1-2 to 1-n. do. At this time, each processor issues a communication request to the bus master 2-2, and the bus master 2-2 arbitrates the requests and grants permission to one processor. The authorized processor is processor no. and output the transfer data onto the bus. Processors 1-1 to 1-n constantly monitor the bus, and processor No. 1 on the bus. The processor that matches the data takes in the data and ends the communication. Further, the processors 1-1 to 1-n read and write data to the memory circuit 8 via the processor interface circuits 4-1 to 4-n. This is normal memory access. Processor interface circuit 4-1 to 4-
n receives requests from processors 1-1 to 1-n via common memory access lines 3-1 to 3-n, respectively;
Access control lines 5-1 to 5 to memory access control circuit 6
-n to make a read or write request. Memory access control circuit 6 is connected to processor interface 4
In response to requests from -1 to 4-n, data is read and written from the memory circuit 8 via the memory bus 7.

0004

[Problems to be Solved by the Invention] However, in such a configuration, in inter-processor communication via the system bus, it is only possible to realize one-to-one communication or broadcast communication between processors; It has been difficult to perform simultaneous communication among multiple sets of processors, such as communicating among the remaining processors while one processor group is communicating. Furthermore, since the amount of data transferred at one time is fixed, there is a drawback that the efficiency is poor in response to increases and decreases in the amount of data transferred.

[0005] Therefore, an object of the present invention is to focus on the fact that a common memory device is connected to all processors in a multiprocessor system, to enable a plurality of groups of processors to perform their respective communications at the same time, and to enable data transfer. It is an object of the present invention to provide a common memory device and a communication control method using the common memory device that can perform efficient transfer even when the amount of transfer increases or decreases.

[0006]

[Means for Solving the Problems] A common memory device of a multiprocessor system according to the present invention has a memory circuit for storing data of a plurality of processors; and a memory circuit for storing data of a plurality of processors. a plurality of processor interface circuits that translate instructions from the processors and identify memory access requests to the memory circuits and interprocessor communication requests to each of the processors; a memory access control circuit that analyzes the memory access request and controls access to the memory circuit; a memory access control circuit that is connected to each of the processor interface circuits and that analyzes the inter-processor communication request from each processor and controls access to the memory circuit; Storing designation information specifying transfer data in correspondence with a communication partner's processor, and outputting an interrupt request requesting each of the communication partner processors to read the transfer data on the memory circuit according to the designation information. and a communication control circuit.

A communication control method for a multiprocessor system according to the present invention comprises connecting a common memory device having the above configuration and a plurality of processors to form a multiprocessor system;
Create specification information specifying transfer data to be transferred from any communication source processor to any other communication partner processor based on data written in advance in the common memory device, and include this specification information. sending instructions from the communicating processor to the common memory device;
This command is analyzed by the common memory device and the designation information is stored corresponding to each of the designated communication partner processors, and the designation information is stored for each of the designated communication partner processors. The method also includes the steps of transmitting an interrupt request, and reading the transfer data from the common memory device for each processor of the communicating party based on the interrupt request.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of a common memory device of the present invention. 1-1 to 1-n are processors, 2-1 is a system bus used for communication between each processor, 2-2 is a bus master that controls inter-processor communication on the system bus, and 3-1 to 3-n are processors A common memory access bus that accesses common memory devices. In the common memory device, 4-1 to 4-n are processor interface circuits that communicate one-on-one with the processors 1-1 to 1-n, respectively, and 5-1 to 5-n are processor interface circuits 4-1 to 4-4. -n and a memory access bus for performing memory access between the memory access control circuit 6; 6 is a processor interface circuit 4-1 to 4-n;
7 is a memory bus through which the memory access control circuit 6 accesses the memory circuit 8; 8 is a memory circuit; 9-1 to 9-n are Communication control lines connecting the processor and common memory, 10-1 to 10-n
are communication data transfer buses 11-1 to 4-n that transfer communication data to processor interface circuits 4-1 to 4-n;
11-n is an in-memory communication control line that controls inter-processor communication within the memory, and 12 is an inter-processor communication control circuit that has communication control registers 12a corresponding to the processors and controls communication between the processors.

Next, in the above configuration, the processor 1
The communication control operation will be explained by taking as an example the case where processor 1-1 communicates with processor 1-2.

The processor 1-1 first has a common memory access bus 3-1 and a processor interface circuit 4-1.
, the memory access bus 5-1, the memory access control circuit 6, and the memory bus 7 to write communication data into the memory circuit 8. Next, the processor 1-1 connects the processor interface circuit 4-1 to the processor No. 4 via the common memory access bus 3-1. Write the start address of the communication data and the number of words. The processor interface circuit 4-1 receives an access request from the processor, determines whether it is a normal memory access or an access for inter-processor communication, and sends the inter-processor communication to the communication control circuit 12 via the in-memory communication control line 11-1. make a request. The communication control circuit 12 is the processor interface circuit 4
-1 to 4-n, and grants communication permission to the selected processor interface circuit 4-1. Permitted processor interface circuit 4-1
is the processor number of the communication partner received from the processor. , the start address, and the number of words are communicated through the data transfer bus 10-1.
The data is transferred to the communication control circuit 12 via. Communication control circuit 1
2 is the destination processor No. 2 from the processor interface circuit 4-1. The communication control circuit 12 analyzes the written communication control register 12a and inputs the start address and number of words into the corresponding communication control register 12a. The in-memory communication control line 11 is connected to the processor interface circuit 4-2 corresponding to the register 12a.
-2 to the processor interface circuit 4-2, and simultaneously transfers the start address and number of words of communication data via the communication data transfer bus 10-2. Processor interface circuit 4-2, which has received the interrupt request, issues a communication interrupt request to processor 1-2 via communication control line 9-2. The processor 1-2 normally performs read access to the processor interface circuit 4-2 as soon as the memory access is completed. The processor interface circuit 4-2 receives the read request from the processor 1-2 from the communication control circuit 12 according to the address and number of words, and accesses the memory circuit 8 via the memory access control circuit 6 in the same manner as normal memory access. Read data from processor 1
Transfer to -2. Processor interface circuit 4-
After completing the transfer, the communication control circuit 12 sends an end signal to the communication control circuit via the in-memory communication control line, and the communication control circuit 12 receives the completion signal through the in-memory communication control line 11-1 and the processor interface circuit 4-. 1. Send a communication end signal to the processor 1-1 via the communication control line 9-1.
Communication between -1 and 1-2 ends.

In this way, since it is not necessary to use the system bus 2-1 for communication (data transfer) between processors, during the period of communication between processors 1-1 and 1-2, other Communication is also possible between any of the remaining processors 1-3 to 1-n. Each processor 1-
The memory access control circuit 6 adjusts the timing of access to the memory circuit 8 from the processor interface circuits 1 to 1-n, that is, the respective processor interface circuits 4-1 to 4-n.

[0013]

[Effects of the Invention] As explained above, according to the present invention,
Not only is one-to-one communication between processors and broadcast communication possible, but also it is possible for one set of processors to perform another communication within the remaining processor group while the other processors are communicating, and it is also possible to transmit data. Since the transfer amount is variable, it has the advantage of being efficient in dealing with increases and decreases in the transfer amount and being able to handle large amounts of data transfer.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of a common memory device of the present invention.

FIG. 2 is a block diagram of a conventional common memory device.

[Explanation of symbols]

1-1 to 1-n Processor 2-1 System bus 2-2 Bus master 3-1 to 3-n Common memory access bus 4-1
~4-n Processor interface circuit 5-
1 to 5-n Memory access bus 6 Memory access control circuit 7 Memory bus 8 Memory circuits 9-1 to 9-n Communication control lines 10-1 to 10-n Communication data transfer bus 11-
1 to 11-n Memory communication control line 12
Communication control circuit 12a Communication control register

Claims (2)

[Claims] 1. A memory circuit for storing data of a plurality of processors; a memory circuit for storing data of a plurality of processors;
a plurality of processor interface circuits that perform pair-to-one communication, translate instructions from the corresponding processors, and identify memory access requests to the memory circuits and interprocessor communication requests to each of the processors; and analyzing the memory access request from each processor;
a memory access control circuit that controls access to the memory circuit; a memory access control circuit that is connected to each of the processor interface circuits, analyzes the inter-processor communication request from each of the processors, and generates specification information that specifies transfer data on the memory circuit; and a communication control circuit that outputs an interrupt request that is stored in correspondence with a processor of a communication partner and requests each of the processors of the communication partner to read the transfer data on the memory circuit according to the specified information. A common memory device for multiprocessor systems. 2. A multiprocessor system is configured by connecting the common memory device according to claim 1 and a plurality of processors, and a multiprocessor system is configured by connecting a common memory device according to claim 1 to a plurality of processors, and transmits data from any communication source processor to another based on data written in advance in the common memory device. Create specification information that specifies transfer data to be transferred to any communication partner processor, send an instruction including this specification information from the communication source processor to the common memory device, and send this instruction to the common memory device. The designation information is analyzed and stored in a memory device corresponding to each of the designated communication partner processors, and an interrupt request is sent to each of the designated communication partner processors together with the stored designation information. A communication control method for a multiprocessor system, characterized in that the transfer data is read from the common memory device for each communication partner processor based on the interrupt request.