JPH01183841A - Lead frame - Google Patents
Lead frameInfo
- Publication number
- JPH01183841A JPH01183841A JP902988A JP902988A JPH01183841A JP H01183841 A JPH01183841 A JP H01183841A JP 902988 A JP902988 A JP 902988A JP 902988 A JP902988 A JP 902988A JP H01183841 A JPH01183841 A JP H01183841A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- lead frame
- base material
- brazing
- metallic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 29
- 239000000463 material Substances 0.000 claims abstract description 21
- 238000007747 plating Methods 0.000 claims abstract description 16
- 238000005219 brazing Methods 0.000 claims abstract description 15
- 229910052751 metal Inorganic materials 0.000 claims description 25
- 239000002184 metal Substances 0.000 claims description 25
- 230000000694 effects Effects 0.000 abstract description 5
- 229910000679 solder Inorganic materials 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83194—Lateral distribution of the layer connectors
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体チップを載置するリードフレームに関
するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a lead frame on which a semiconductor chip is mounted.
従来樹脂封止型半導体装置の組立て工程は、半導体ウェ
ハ上に形成された多数の半導体チップを個々の半導体チ
ップに切断、分離した後、これを銀等の金属めっきの形
成されたリードフレームのアイランド上にハンダ等の金
属ろう材によってろう付けするいわゆるダイポンド工程
を有する。Conventionally, the assembly process for resin-encapsulated semiconductor devices involves cutting and separating a large number of semiconductor chips formed on a semiconductor wafer into individual semiconductor chips, and then inserting them into islands of a lead frame plated with metal such as silver. It has a so-called die-pond process in which it is brazed with a metal brazing material such as solder.
この従来のグイボンド工程において使用されていたリー
ドフレームは、アイランド全面に金属めっきが形成され
ているために、半導体チップの裏面の全面がアイランド
とろう付けされ、温度環境の変化に伴い、リードフレー
ム材と半導体チップの熱膨張率の差により半導体チップ
に過大な応力が加わるという問題点があった。The lead frame used in the conventional Guibond process has metal plating formed on the entire surface of the island, so the entire back surface of the semiconductor chip is brazed to the island, and as the temperature environment changes, the lead frame material There is a problem in that excessive stress is applied to the semiconductor chip due to the difference in thermal expansion coefficient between the semiconductor chip and the semiconductor chip.
この発明は、このような従来のものの問題点を解消する
ためになされたもので、半導体チップとアイランド間の
接合面積および箇所を容易に制御可能なリードフレーム
を提供することを目的とする。The present invention has been made to solve the problems of the conventional devices, and an object of the present invention is to provide a lead frame in which the bonding area and location between a semiconductor chip and an island can be easily controlled.
この発明に係るリードフレームは、金属めっき膜が施さ
れているアイランド部に部分的に酸化被膜を形成し、こ
の酸化被膜が形成されている部分以外の部分の金属めっ
き膜に金属ろう材によって半導体チップをろう付けする
よう構成されたものである。In the lead frame according to the present invention, an oxide film is partially formed on the island portion on which the metal plating film is applied, and the metal plating film in the part other than the part where the oxide film is formed is applied to the semiconductor by using a metal brazing material. It is configured to braze chips.
この発明における酸化被膜は、金属ろう材に対して濡れ
ないため、この部分では金属ろう材によるろう付けがな
されず、半導体チップがリードフレームのアイランド母
材に部分的にろう付けされるので、温度変化による半導
体チップに対する応力の影響が軽減される。Since the oxide film in this invention does not wet the metal brazing material, brazing with the metal brazing material is not performed in this part, and the semiconductor chip is partially brazed to the island base material of the lead frame. The effect of stress on the semiconductor chip due to changes is reduced.
以下この発明の一実施例を第１図〜第３図にもとづいて
説明する。An embodiment of the present invention will be described below with reference to FIGS. 1 to 3.
即ち図において、１は放電用電源、２は放電用電源に接
続された電極、３はリードフレームのアイランド母材４
上に形成された金属めっき膜、５は電極２と放電５を発
生させ、アイランド母材４との間に発生させた放電によ
って金属めっき膜３上に形成された酸化被膜、６はアイ
ランド母材４の金属めっき膜３上に金属ろう材７によっ
て取付けられた半導体チップである。ここで半導体チッ
プ６は金属ろう材５によって酸化被膜５のない箇所にお
いてのみ金属めっき膜３に接合されている。That is, in the figure, 1 is a discharge power source, 2 is an electrode connected to the discharge power source, and 3 is an island base material 4 of the lead frame.
The metal plating film 5 is formed on the metal plating film 3, 5 is an oxide film formed on the metal plating film 3 by the discharge generated between the electrode 2 and the island base material 4, and 6 is the island base material. This is a semiconductor chip mounted on the metal plating film 3 of No. 4 with a metal brazing material 7. Here, the semiconductor chip 6 is bonded to the metal plating film 3 by the metal brazing material 5 only at locations where the oxide film 5 is not present.
即ち酸化被膜の形成されたアイランド上の金属めっき膜
は金属ろう材に対し濡れないため半導体チップとろう付
けされない。また高電圧放電に用いる電極の形状を変え
ることによって、ろう付けを行わない面積および個所を
容易に制御することが可能となる。That is, the metal plating film on the island on which the oxide film is formed is not wetted by the metal brazing material, and therefore is not brazed to the semiconductor chip. Furthermore, by changing the shape of the electrode used for high voltage discharge, it becomes possible to easily control the areas and locations where brazing is not performed.
このように半導体チップ６をアイランド母材４の金属め
っき膜３に部分的に接合しているので、半導体チップと
リードフレームの熱膨張率の差が金属ろう付けで吸収さ
れ、温度環境の変化に伴う半導体チップに加わる過大な
応力を避けることができる。Since the semiconductor chip 6 is partially bonded to the metal plating film 3 of the island base material 4 in this way, the difference in thermal expansion coefficient between the semiconductor chip and the lead frame is absorbed by the metal brazing, and it is resistant to changes in the temperature environment. Accordingly, excessive stress applied to the semiconductor chip can be avoided.
上記のようにこの発明によるリードフレームは、半導体
チップとリードフレームのアイランド母材とは、部分的
にろう付けされるよう構成されているので、温度変化に
よる半導体チップへの応力の影響を軽減することができ
る。As described above, the lead frame according to the present invention is configured such that the semiconductor chip and the island base material of the lead frame are partially brazed, thereby reducing the influence of stress on the semiconductor chip due to temperature changes. be able to.
第１図〜第３図はいずれもこの発明の二実施例を示す図
で、第１図は製造工程途中の状態を示す概略側面図、第
２図は要部拡大斜視図、第３図は半導体チップが取付け
られた状態を示す要部拡大側面図である。
図中、１は放電電源、２は電極、３は金属めっき膜、４
はアイランド母材、５は酸化被膜、６は半導体チップ、
７は金属ろう材である。
尚、図中同一符号は同−又は相当部分を示す。Figures 1 to 3 are views showing two embodiments of the present invention. Figure 1 is a schematic side view showing a state in the middle of the manufacturing process, Figure 2 is an enlarged perspective view of the main part, and Figure 3 is a diagram showing two embodiments of the present invention. FIG. 2 is an enlarged side view of a main part showing a state in which a semiconductor chip is attached. In the figure, 1 is a discharge power supply, 2 is an electrode, 3 is a metal plating film, and 4
is an island base material, 5 is an oxide film, 6 is a semiconductor chip,
7 is a metal brazing material. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
ンド部の金属めっき面に部分的に形成された酸化被膜を
備え、上記酸化被膜の形成されている部分以外の金属め
っき部に金属ろう材を介して半導体チップをろう付けす
るよう形成されてなるリードフレーム。An island portion on which metal plating is applied, an oxide film partially formed on the metal plating surface of this island portion, and a metal brazing material applied to the metal plating portion other than the portion where the oxide film is formed. A lead frame formed to braze semiconductor chips.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP902988A JPH01183841A (en) | 1988-01-18 | 1988-01-18 | Lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP902988A JPH01183841A (en) | 1988-01-18 | 1988-01-18 | Lead frame |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01183841A true JPH01183841A (en) | 1989-07-21 |
Family
ID=11709228
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP902988A Pending JPH01183841A (en) | 1988-01-18 | 1988-01-18 | Lead frame |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01183841A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5341564A (en) * | 1992-03-24 | 1994-08-30 | Unisys Corporation | Method of fabricating integrated circuit module |
-
1988
- 1988-01-18 JP JP902988A patent/JPH01183841A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5341564A (en) * | 1992-03-24 | 1994-08-30 | Unisys Corporation | Method of fabricating integrated circuit module |
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