JPH0117298B2 - - Google Patents

Info

Publication number
JPH0117298B2
JPH0117298B2 JP56119716A JP11971681A JPH0117298B2 JP H0117298 B2 JPH0117298 B2 JP H0117298B2 JP 56119716 A JP56119716 A JP 56119716A JP 11971681 A JP11971681 A JP 11971681A JP H0117298 B2 JPH0117298 B2 JP H0117298B2
Authority
JP
Japan
Prior art keywords
staff
circuit
synchronization
frequency
control circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56119716A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5820046A (ja
Inventor
Tetsuo Murase
Takashi Wakabayashi
Hisanobu Fujimoto
Masahiro Shinbashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11971681A priority Critical patent/JPS5820046A/ja
Publication of JPS5820046A publication Critical patent/JPS5820046A/ja
Publication of JPH0117298B2 publication Critical patent/JPH0117298B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
    • H04J3/073—Bit stuffing, e.g. PDH

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
JP11971681A 1981-07-30 1981-07-30 スタツフ同期方式 Granted JPS5820046A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11971681A JPS5820046A (ja) 1981-07-30 1981-07-30 スタツフ同期方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11971681A JPS5820046A (ja) 1981-07-30 1981-07-30 スタツフ同期方式

Publications (2)

Publication Number Publication Date
JPS5820046A JPS5820046A (ja) 1983-02-05
JPH0117298B2 true JPH0117298B2 (de) 1989-03-29

Family

ID=14768338

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11971681A Granted JPS5820046A (ja) 1981-07-30 1981-07-30 スタツフ同期方式

Country Status (1)

Country Link
JP (1) JPS5820046A (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5699759B2 (ja) * 2011-04-01 2015-04-15 富士通株式会社 伝送装置及び伝送方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5685948A (en) * 1979-12-14 1981-07-13 Fujitsu Ltd Stuffing synchronizing system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5685948A (en) * 1979-12-14 1981-07-13 Fujitsu Ltd Stuffing synchronizing system

Also Published As

Publication number Publication date
JPS5820046A (ja) 1983-02-05

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