JPH01171548U

JPH01171548U -

Info

Publication number: JPH01171548U
Application number: JP6864688U
Authority: JP
Priority date: 1988-05-23
Filing date: 1988-05-23
Publication date: 1989-12-05

Description

[Brief explanation of the drawing]

第１図は本考案パツケージの第１実施例の構成
を示すブロツク図、第２図はその斜視図、第３図
及び第４図は本考案パツケージの第１実施例の各
構成を示す接続図、第５図は本考案パツケージの
第２実施例の構成を示す接続図、第６図は本考案
パツケージの第３実施例の構成を示すブロツク図
、第７図はその斜視図、第８図は第３実施例の構
成を示す接続図、第９図は本考案パツケージの第
４実施例の構成を示すブロツク図、第１０図は第
４実施例の構成を示す回路図である。１……充電回路、２……二次電池、３……電圧
検出用ＩＣを用いた電圧検出回路、４……電源供
給回路、５……メモリプロテクトロジツク回路、
Ｄ_１，Ｄ_２……ダイオード、ＣＰＵ……中央処理
装置、Ｍ……メモリ。 Fig. 1 is a block diagram showing the structure of the first embodiment of the package of the present invention, Fig. 2 is a perspective view thereof, and Figs. 3 and 4 are connection diagrams showing the respective structures of the first embodiment of the package of the present invention. , FIG. 5 is a connection diagram showing the structure of the second embodiment of the package of the present invention, FIG. 6 is a block diagram showing the structure of the third embodiment of the package of the present invention, FIG. 7 is a perspective view thereof, and FIG. 8 9 is a connection diagram showing the structure of the third embodiment, FIG. 9 is a block diagram showing the structure of the fourth embodiment of the package of the present invention, and FIG. 10 is a circuit diagram showing the structure of the fourth embodiment. DESCRIPTION OF SYMBOLS 1... Charging circuit, 2... Secondary battery, 3... Voltage detection circuit using voltage detection IC, 4... Power supply circuit, 5... Memory protection logic circuit,
_D1 , _D2 ...Diode, CPU...Central processing unit, M...Memory.

Claims

[Claims for Utility Model Registration] (1) A charging circuit 1 that inputs a DC voltage Vi and outputs a charging voltage Vz via a diode _D2 ;
A small secondary battery 2 that is constantly charged with a charging voltage Vz, a voltage detection circuit 3 using a voltage detection IC that detects when the DC voltage Vi has fallen below an allowable range, and a power supply circuit 4 that cuts off the power supplied to the memory M based on the output; a diode _D1 that supplies the voltage of the secondary battery 2 to the memory M when the power to the memory M is cut off by this circuit 4; A charging function that includes a memory protection logic circuit 5 that protects the memory M by prohibiting the write operation of the memory M based on the output obtained from the power supply circuit 4 when the DC voltage Vi falls below an allowable range. Comes with secondary battery package. (2) a charging circuit 1 that inputs a DC voltage Vi and outputs a charging voltage Vz via a diode _D2 ;
A small secondary battery 2 that is constantly charged with a charging voltage Vz, a voltage detection circuit 3 using a voltage detection IC that detects when the DC voltage Vi has fallen below an allowable range, and A power supply circuit 4 that cuts off the power supplied to the memory M based on the output; and a diode D1 that supplies the voltage of the secondary battery 2 to the memory M when the power to the memory M is cut off by this circuit ₄ . , and a memory protection logic circuit 5 which protects the memory M by inhibiting write operation of the memory M based on a signal from a central processing unit CPU. (3) a charging circuit 1 that inputs a DC voltage Vi and outputs a charging voltage Vz via a diode _D2 ;
A small secondary battery 2 that is constantly charged with a charging voltage Vz, a voltage detection circuit 3 using a voltage detection IC that detects when the DC voltage Vi has fallen below an allowable range, and A power supply circuit 4 that cuts off the power supplied to the memory M based on the output, a diode _D1 that supplies the voltage of the secondary battery 2 to the memory M when the power to the memory M is cut off by this circuit 4, and a power supply. A secondary battery package with a charging function is packed with a memory protection logic circuit 5 which protects the memory M by inhibiting write operation of the memory M based on the output from the supply circuit 4 and the signal from the central processing unit CPU. (4) a charging circuit 1 that inputs a DC voltage Vi and outputs a charging voltage Vz via a diode _D2 ;
A small secondary battery 2 that is constantly charged with a charging voltage Vz, a voltage detection circuit 3 using a voltage detection IC that detects when the DC voltage Vi has fallen below an allowable range, and a power supply circuit 4 that cuts off the power supplied to the memory M based on the output; a diode _D1 that supplies the voltage of the secondary battery 2 to the memory M when the power to the memory M is cut off by this circuit 4; The output from the voltage detection circuit 3 inhibits the write operation of the memory M.
A secondary battery package with a charging function is packed with a memory protection logic circuit 5 for protecting the memory. (5) a charging circuit 1 that inputs a DC voltage Vi and outputs a charging voltage Vz via a diode _D2 ;
A small secondary battery 2 that is constantly charged with a charging voltage Vz, a voltage detection circuit 3 using a voltage detection IC that detects when the DC voltage Vi has fallen below an allowable range, and a power supply circuit 4 that cuts off the power supplied to the memory M based on the output; a diode D ₁ that supplies the voltage of the secondary battery 2 to the memory M when the power to the memory M is cut off by this circuit 4; A memory protection technology that protects the memory M when the DC voltage Vi falls below the allowable range, and continues to prohibit write operations to the memory M for a predetermined period of time based on the output of a reset circuit when the DC voltage Vi returns to within the allowable range. This is a secondary battery package with a charging function, which is made up of a power supply circuit 5 and a power supply circuit 5.