JPH02138321U

JPH02138321U -

Info

Publication number: JPH02138321U
Application number: JP4713089U
Authority: JP
Priority date: 1989-04-21
Filing date: 1989-04-21
Publication date: 1990-11-19

Description

[Brief explanation of the drawing]

第１図ａ，ｂはそれぞれ本考案パツケージの第
１実施例の構成を示すブロツク図及びその斜視図
、第２図は第１実施例の回路図、第３図は第２実
施例の回路図、第４図ａ，ｂはそれぞれ第３実施
例の構成を示すブロツク図及びその斜視図、第５
図は第３実施例の回路図、第６図は第４実施例の
回路図、第７図は第５実施例の回路図、第８図は
第６実施例の回路図、第９図は第７実施例のブロ
ツク図、第１０図は第７実施例の回路図、第１１
図は第８実施例の回路図、第１２図は第９実施例
の回路図、第１３図は第１０実施例の構成を示す
ブロツク図、第１４図は第１０実施例の回路図、
第１５図は第１１実施例の構成を示すブロツク図
、第１６図は第１１実施例の接続図、第１７図は
本考案パツケージの一例を示す縦断面図である。Ｖｉ……直流電圧、Ｒ_５，Ｒ_６……抵抗、Ｖ_０……作動用電圧、Ｖｚ……充電用電圧、Ｄ１，Ｄ
２……ダイオード、１……充電回路、２……二次
電池、Ｍ……メモリ、３……電源監視回路、３ａ
……電圧検出回路（電圧検出用ＩＣ）、３ｂ……
電源供給回路、４……リセツト回路、５……メモ
リプロテクトロジツク回路、６……停電検出回路
、ＣＰＵ……中央処理装置、７……回路基板、８
……外ケース、９……樹脂部、１０……ガス抜き
穴、１１……本考案パツケージ、１２……一次電
源検出器、１３……電圧検出回路、１４……回路
部品、１５……端子用ピン。 1A and 1B are block diagrams and perspective views thereof showing the structure of the first embodiment of the package of the present invention, FIG. 2 is a circuit diagram of the first embodiment, and FIG. 3 is a circuit diagram of the second embodiment. , FIGS. 4a and 4b are a block diagram and a perspective view thereof showing the configuration of the third embodiment, respectively, and FIG.
The figure is a circuit diagram of the third embodiment, Figure 6 is a circuit diagram of the fourth embodiment, Figure 7 is a circuit diagram of the fifth embodiment, Figure 8 is a circuit diagram of the sixth embodiment, and Figure 9 is a circuit diagram of the fourth embodiment. FIG. 10 is a block diagram of the seventh embodiment, FIG. 10 is a circuit diagram of the seventh embodiment, and FIG.
12 is a circuit diagram of the ninth embodiment, FIG. 13 is a block diagram showing the configuration of the tenth embodiment, FIG. 14 is a circuit diagram of the tenth embodiment,
FIG. 15 is a block diagram showing the configuration of the eleventh embodiment, FIG. 16 is a connection diagram of the eleventh embodiment, and FIG. 17 is a longitudinal sectional view showing an example of the package of the present invention. Vi...DC voltage, _R5 , _R6 ...Resistance, _V0 ...Operating voltage, Vz...Charging voltage, D1, D
2...Diode, 1...Charging circuit, 2...Secondary battery, M...Memory, 3...Power supply monitoring circuit, 3a
...Voltage detection circuit (voltage detection IC), 3b...
Power supply circuit, 4...Reset circuit, 5...Memory protection logic circuit, 6...Power failure detection circuit, CPU...Central processing unit, 7...Circuit board, 8
... Outer case, 9 ... Resin part, 10 ... Gas vent hole, 11 ... Package of the present invention, 12 ... Primary power supply detector, 13 ... Voltage detection circuit, 14 ... Circuit component, 15 ... Terminal pin.

Claims

[Claims for Utility Model Registration] (1) Input DC voltage Vi, resistor _R5 and resistor _R6
A charging circuit 1 outputs the divided voltage using the voltage Vz as a charging voltage Vz through a diode D2, a small secondary battery 2 that is constantly charged by the charging voltage Vz, and A power supply monitoring circuit 3 detects that the voltage has dropped and switches the power supply to the memory M from the DC voltage Vi to the secondary battery 2; 2 with a charging function, which is made by modularizing a diode D1 supplied to the memory M and a memory protection logic circuit 5 which outputs a signal to inhibit the write operation of the memory M and protect the memory M based on the output of the power supply monitoring circuit 3. Next battery package. (2) Input DC voltage Vi, resistor _R5 and resistor R A charging circuit 1 that outputs a voltage divided using ₆ as a charging voltage Vz through a diode D2.
, a small secondary battery 2 that is constantly charged by the charging voltage Vz, and detecting that the DC voltage Vi has fallen below the allowable range, changes the power supply to the memory M from the DC voltage Vi to the secondary battery 2. a power supply monitoring circuit 3 that switches to the power supply monitoring circuit 3, a diode D1 that supplies the voltage of the secondary battery 2 to the memory M when the DC voltage Vi falls below the allowable range, and a signal from the central processing unit CPU based on the output of the power failure detection circuit 6. A secondary battery package with a charging function is formed by modularizing a memory protection logic circuit 5 which outputs a signal to protect a memory M based on the memory M. (3) Input DC voltage Vi, resistor _R5 and resistor R A charging circuit 1 that outputs a voltage divided using ₆ as a charging voltage Vz through a diode D2.
, a small secondary battery 2 that is constantly charged by the charging voltage Vz, and detecting that the DC voltage Vi has fallen below the allowable range, changes the power supply to the memory M from the DC voltage Vi to the secondary battery 2. a diode D1 that supplies the voltage of the secondary battery 2 to the memory M when the DC voltage Vi falls below the allowable range; and a diode D1 that supplies the voltage of the secondary battery 2 to the memory M when the power supply voltage is restored.
A memory protection logic circuit that outputs a signal that protects the memory M by the reset signal output from the reset circuit 4 that outputs a reset signal that prohibits writing to the memory M and cancels the reset signal after a certain time delay until the power supply voltage is restored. A secondary battery package with charging function made by modularizing 5. (4) A secondary battery package with a charging function according to claim 3, further comprising a reset circuit 4. (5) The power supply monitoring circuit 3 includes a voltage detection circuit 3 that detects that the DC voltage Vi has fallen below an allowable range.
A secondary battery package with a charging function according to any one of claims 1 to 4, comprising a power supply circuit (3b) that cuts off power supply to the memory (M) based on the output of the circuit (3). (6) The memory protection logic circuit 5 detects an abnormality in the power supply and sends this detection signal to the reset circuit 4.
and the reset signal of the central processing unit CPU.
A signal that is input to the terminal and terminal of , saves the processed data to the memory M by the processing routine, and further executes and stops the process by the central processing unit CPU, and then inputs that signal and protects the memory M based on the signal. Claims 3 and 4 are circuits that output
A secondary battery package with a charging function as described in any of the above. (7) The memory protection logic circuit 5 includes a primary power supply detector 12 or voltage detection circuit 13 that detects abnormality in the power supply, this detection signal, and a reset circuit 4.
and the reset signal of the central processing unit CPU.
After inputting the signal to the terminal and the terminal, the processing data is saved in the memory M by the processing routine, and after the central processing unit CPU executes and stops, the signal is input and the memory M is protected based on it. The secondary battery package with a charging function according to claim 3, which is a circuit that outputs a signal. (8) The secondary battery 2 and the circuit board 7 formed with the required circuit are laminated.
The secondary battery package with a charging function according to any one of Item 7. (9) The outer case 8 molded from thermoplastic resin covers the secondary battery 2 and the circuit board 7, and the lower surface of the outer case 8 is formed with a resin part 9 mainly composed of epoxy resin. A secondary battery package with a charging function according to any one of items 1 to 8. (10) Claim 9, wherein the circuit board 5 is provided with a gas vent hole 10 for venting gas during formation of the resin portion 9.
Secondary battery package with charging function as described in section.