JPH0191950U - - Google Patents
Info
- Publication number
- JPH0191950U JPH0191950U JP18850187U JP18850187U JPH0191950U JP H0191950 U JPH0191950 U JP H0191950U JP 18850187 U JP18850187 U JP 18850187U JP 18850187 U JP18850187 U JP 18850187U JP H0191950 U JPH0191950 U JP H0191950U
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- memory
- secondary battery
- charging
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000014759 maintenance of location Effects 0.000 claims description 2
- 238000012544 monitoring process Methods 0.000 claims description 2
- 230000005856 abnormality Effects 0.000 claims 1
- 238000001514 detection method Methods 0.000 claims 1
- 230000006870 function Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Stand-By Power Supply Arrangements (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Emergency Protection Circuit Devices (AREA)
Description
第１図は本考案パツケージの基本構成を示すブ
ロツク図、第２図は本考案パツケージの斜視図、
第３図は本考案パツケージの一実施例の構成を示
す接続図である。
１……充電回路、２……二次電池、３……ダイ
オード、４……電源監視回路、５……メモリプロ
テクトロジツク回路、６……本考案パツケージ、
Ｖｉ……直流電圧、Ｖｚ……充電用電圧、Ｖｏ…
…メモリ作動電圧ないし記憶保持用電圧、Ｍ……
メモリ、ＣＰＵ……中央処理装置。
Figure 1 is a block diagram showing the basic structure of the package of the present invention, Figure 2 is a perspective view of the package of the present invention,
FIG. 3 is a connection diagram showing the structure of one embodiment of the package of the present invention. DESCRIPTION OF SYMBOLS 1... Charging circuit, 2... Secondary battery, 3... Diode, 4... Power monitoring circuit, 5... Memory protection logic circuit, 6... Package of the present invention,
Vi...DC voltage, Vz...Charging voltage, Vo...
...Memory operating voltage or memory retention voltage, M...
Memory, CPU...Central processing unit.
Claims (1)
Ｍの作動用電圧Ｖｏを出力する充電回路１と、充
電用電圧Ｖｚにより常時、充電される小型の二次
電池２と、直流電圧Ｖｉが許容範囲以下に低下し
た時にこの二次電池２の電圧を上記メモリＭに供
給して記憶保持に供するダイオード３と、直流電
圧Ｖｉが許容範囲以下に低下したことを検出する
電源監視回路４と、電源監視回路４の出力と異常
検出機構の出力を入力してそれに基づいてメモリ
Ｍをプロテクトする信号を出力するメモリプロテ
クトロジツク回路５とをパツクしてなるコンピユ
ータ用充電機能付き二次電池パツケージ。 A charging circuit 1 that inputs a DC voltage Vi and outputs a charging voltage Vz and an operating voltage Vo for the memory M, a small secondary battery 2 that is constantly charged by the charging voltage Vz, and a DC voltage Vi within an allowable range. a diode 3 that supplies the voltage of the secondary battery 2 to the memory M for memory retention when the voltage of the secondary battery 2 drops below a voltage range of 20 to 300 nm, a power supply monitoring circuit 4 that detects that the DC voltage Vi has fallen below an allowable range; This is a secondary battery package for a computer with a charging function, which is packed with a memory protection logic circuit 5 which inputs the output of a circuit 4 and the output of an abnormality detection mechanism and outputs a signal to protect a memory M based on the input.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18850187U JPH0191950U (en) | 1987-12-11 | 1987-12-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18850187U JPH0191950U (en) | 1987-12-11 | 1987-12-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0191950U true JPH0191950U (en) | 1989-06-16 |
Family
ID=31479589
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18850187U Pending JPH0191950U (en) | 1987-12-11 | 1987-12-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0191950U (en) |
-
1987
- 1987-12-11 JP JP18850187U patent/JPH0191950U/ja active Pending
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