JPH0191949U - - Google Patents
Info
- Publication number
- JPH0191949U JPH0191949U JP18850087U JP18850087U JPH0191949U JP H0191949 U JPH0191949 U JP H0191949U JP 18850087 U JP18850087 U JP 18850087U JP 18850087 U JP18850087 U JP 18850087U JP H0191949 U JPH0191949 U JP H0191949U
- Authority
- JP
- Japan
- Prior art keywords
- memory
- voltage
- secondary battery
- charging
- diode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000014759 maintenance of location Effects 0.000 claims 2
- 230000006870 function Effects 0.000 claims 1
- 230000002401 inhibitory effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
- Emergency Protection Circuit Devices (AREA)
- Stand-By Power Supply Arrangements (AREA)
Description
第１図は本考案パツケージの基本構成を示すブ
ロツク図、第２図は本考案パツケージの斜視図、
第３図は本考案パツケージの一実施例の構成を示
す接続図である。
１……充電回路、２……二次電池、３……ダイ
オード、４……メモリプロテクトロジツク回路、
５……本考案パツケージ、Ｖｉ……直流電圧、Ｖ
ｚ……充電用電圧、Ｖｏ……メモリ作動用電圧、
Ｍ……メモリ、ＣＰＵ……中央処理装置。
Figure 1 is a block diagram showing the basic configuration of the package of the present invention, Figure 2 is a perspective view of the package of the present invention,
FIG. 3 is a connection diagram showing the structure of one embodiment of the package of the present invention. 1... Charging circuit, 2... Secondary battery, 3... Diode, 4... Memory protection logic circuit,
5...Package of the present invention, Vi...DC voltage, V
z...Charging voltage, Vo...Memory operating voltage,
M...Memory, CPU...Central processing unit.
Claims (1)
Ｍの作動用電圧Ｖｏを出力する充電回路１と、充
電用電圧Ｖｚにより常時、充電される小型の二次
電池２と、直流電圧Ｖｉが許容範囲以下に低下し
た時にこの二次電池２の電圧を上記メモリＭに供
給して記憶保持に供するダイオード３と、メモリ
プロテクトの端子に交流電源を監視する電源監視
回路の出力信号を入力してメモリＭの書き込み動
作を禁止し、メモリＭをプロテクトする信号を出
力するメモリプロテクトロジツク回路４とをパツ
クしてなるコンピユータ用充電機能付き二次電池
パツケージ。 A charging circuit 1 that inputs a DC voltage Vi and outputs a charging voltage Vz and an operating voltage Vo for the memory M, a small secondary battery 2 that is constantly charged by the charging voltage Vz, and a DC voltage Vi that is within an allowable range. A diode 3 supplies the voltage of the secondary battery 2 to the memory M for memory retention when the voltage of the secondary battery 2 drops below 100 kHz, and a diode 3 supplies the voltage of the secondary battery 2 to the memory M for memory retention, and a memory M This is a secondary battery package for a computer with a charging function, which is packed with a memory protection logic circuit 4 which outputs a signal for inhibiting write operation of the memory M and outputting a signal to protect the memory M.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18850087U JPH0191949U (en) | 1987-12-11 | 1987-12-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18850087U JPH0191949U (en) | 1987-12-11 | 1987-12-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0191949U true JPH0191949U (en) | 1989-06-16 |
Family
ID=31479588
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18850087U Pending JPH0191949U (en) | 1987-12-11 | 1987-12-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0191949U (en) |
-
1987
- 1987-12-11 JP JP18850087U patent/JPH0191949U/ja active Pending
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