JPH0191948U - - Google Patents
Info
- Publication number
- JPH0191948U JPH0191948U JP18849987U JP18849987U JPH0191948U JP H0191948 U JPH0191948 U JP H0191948U JP 18849987 U JP18849987 U JP 18849987U JP 18849987 U JP18849987 U JP 18849987U JP H0191948 U JPH0191948 U JP H0191948U
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- memory
- secondary battery
- charging
- outputs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012544 monitoring process Methods 0.000 claims description 2
- 230000014759 maintenance of location Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
- Emergency Protection Circuit Devices (AREA)
- Stand-By Power Supply Arrangements (AREA)
Description
第１図は本考案パツケージの基本構成を示すブ
ロツク図、第２図は本考案パツケージの斜視図、
第３図は本考案パツケージの一実施例の構成を示
す接続図である。
１……充電回路、２……二次電池、３……ダイ
オード、４……電源監視回路、５……メモリプロ
テクトロジツク回路、６……本考案パツケージ、
Ｖｉ……直流電圧、Ｖｚ……充電用電圧、Ｖｏ…
…メモリ作動用電圧、Ｍ……メモリ。
Figure 1 is a block diagram showing the basic configuration of the package of the present invention, Figure 2 is a perspective view of the package of the present invention,
FIG. 3 is a connection diagram showing the structure of one embodiment of the package of the present invention. DESCRIPTION OF SYMBOLS 1... Charging circuit, 2... Secondary battery, 3... Diode, 4... Power monitoring circuit, 5... Memory protection logic circuit, 6... Package of the present invention,
Vi...DC voltage, Vz...Charging voltage, Vo...
...Memory operating voltage, M...Memory.
Claims (1)
Ｍの作動用電圧Ｖｏを出力する充電回路１と、充
電用電圧Ｖｚにより常時、充電される小型の二次
電池２と、直流電圧Ｖｉが許容範囲以下に低下し
た時にこの二次電池２の電圧を上記メモリＭに供
給して記憶保持に供するダイオード３と、直流電
圧Ｖｉが許容範囲以下に低下したことを検出する
、電源監視回路４と、この電源監視回路４の出力
に基づいてメモリＭの書き込み動作を禁止し、メ
モリＭをプロテクトする信号を出力するメモリプ
ロテクトロジツク回路５とをパツクしてなるコン
ピユータ用充電機能付き二次電池パツケージ。 A charging circuit 1 that inputs a DC voltage Vi and outputs a charging voltage Vz and an operating voltage Vo for the memory M, a small secondary battery 2 that is constantly charged by the charging voltage Vz, and a DC voltage Vi within an allowable range. a diode 3 that supplies the voltage of the secondary battery 2 to the memory M for memory retention when the voltage of the secondary battery 2 drops below a permissible range; This secondary battery package for a computer is equipped with a memory protection logic circuit 5 which inhibits write operation of a memory M based on the output of a power supply monitoring circuit 4 and outputs a signal to protect the memory M.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18849987U JPH0191948U (en) | 1987-12-11 | 1987-12-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18849987U JPH0191948U (en) | 1987-12-11 | 1987-12-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0191948U true JPH0191948U (en) | 1989-06-16 |
Family
ID=31479587
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18849987U Pending JPH0191948U (en) | 1987-12-11 | 1987-12-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0191948U (en) |
-
1987
- 1987-12-11 JP JP18849987U patent/JPH0191948U/ja active Pending
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