JPH01167079U - - Google Patents

Info

Publication number
JPH01167079U
JPH01167079U JP5233489U JP5233489U JPH01167079U JP H01167079 U JPH01167079 U JP H01167079U JP 5233489 U JP5233489 U JP 5233489U JP 5233489 U JP5233489 U JP 5233489U JP H01167079 U JPH01167079 U JP H01167079U
Authority
JP
Japan
Prior art keywords
board
circuit board
wiring
pattern formed
solder bumps
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5233489U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP5233489U priority Critical patent/JPH01167079U/ja
Publication of JPH01167079U publication Critical patent/JPH01167079U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Combinations Of Printed Boards (AREA)

Description

【図面の簡単な説明】
第1図は本考案の一実施例を示す図である。 図において、1,7は回路基板、3は素子、4
は一側面の配線パターン、6は他側面の配線パタ
ーン、8はハンダバンプである。

Claims (1)

    【実用新案登録請求の範囲】
  1. 一側基板面に形成された配線パターンと他側基
    板面に形成された配線パターンとが配線孔を介し
    て接続されている剛性の同路基板を複数枚積層し
    て積層回路基板を形成する際に、その対向基板面
    上に配線パターン間を接続する配線パターン対応
    箇所にハンダバンプを設け、これらハンダバンプ
    を溶着し、電気的接続を前記複数枚の剛性の回路
    基板間に形成して成ることを特徴とする積層回路
    基板。
JP5233489U 1989-05-02 1989-05-02 Pending JPH01167079U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5233489U JPH01167079U (ja) 1989-05-02 1989-05-02

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5233489U JPH01167079U (ja) 1989-05-02 1989-05-02

Publications (1)

Publication Number Publication Date
JPH01167079U true JPH01167079U (ja) 1989-11-22

Family

ID=31278334

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5233489U Pending JPH01167079U (ja) 1989-05-02 1989-05-02

Country Status (1)

Country Link
JP (1) JPH01167079U (ja)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56150897A (en) * 1980-04-23 1981-11-21 Fujitsu Ltd Method of manufacturing multilayer printed board

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56150897A (en) * 1980-04-23 1981-11-21 Fujitsu Ltd Method of manufacturing multilayer printed board

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