JPS6284973U - - Google Patents

Info

Publication number
JPS6284973U
JPS6284973U JP1985176877U JP17687785U JPS6284973U JP S6284973 U JPS6284973 U JP S6284973U JP 1985176877 U JP1985176877 U JP 1985176877U JP 17687785 U JP17687785 U JP 17687785U JP S6284973 U JPS6284973 U JP S6284973U
Authority
JP
Japan
Prior art keywords
conductor
pad
conductor layer
wiring board
printed wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1985176877U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1985176877U priority Critical patent/JPS6284973U/ja
Priority to US06/929,819 priority patent/US4692843A/en
Publication of JPS6284973U publication Critical patent/JPS6284973U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H05K3/462—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar double-sided circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0272—Adaptations for fluid transport, e.g. channels, holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/1025—Metallic discs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
    • H05K2201/2036—Permanent spacer or stand-off in a printed circuit or printed circuit assembly
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4623—Manufacturing multilayer circuits by laminating two or more circuit boards the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs

Description

【図面の簡単な説明】
第１図ａ，ｂは本考案の実施例の要部を示す斜
視図ａと側面図ｂ、第２図は第１図ａの矢位Ｂ平
面図、第３図は第１図のパツド２３の接続導体２
３ｃを切断した状態を示す図、第４図は本考案に
係わるパツド２３の形成工程の説明図、第５図は
従来例の説明図である。 第１，２，３，４図において、２１は多層プリ
ント配線板、２２はスルーホール、２３はパツド
、２３ａは第１導体層、２３ｂは第２導体層、２
３ｃは接続導体、２３ｄは絶縁層、２４は接続パ
ターン、２５はフラツトリード付電子部品、２６
はパツケージ、２７はフラツトリード、３１は第
１のレジスト層（レジストフイルム）、３２は第
２のレジスト層（レジストフイルム）、をそれぞ
れ示す。

Claims (1)

  1. 【実用新案登録請求の範囲】 フラツドリード付電子部品２５のフラツトリー
    ド２７を固着するためのパツド２３と、該パツド
    ２３をスルーホール２２に接続するための接続パ
    ターン２４を有する多層プリント配線板２１であ
    つて、 上記パツド２３を、上記プリント配線板２１上
    に形成した第１導体層２３ａと、該第１導体層２
    ３ａ上方に間隙を介して配設した第２導体層２３
    ｂと、これら第１、第２導体層２３ａ，２３ｂに
    おける上記接続パターン２４側を除く外周部の一
    部同士相互間を接続する上下方向の接続導体２３
    ｃと、上記第１、第２導体層２３ａ，２３ｂ相互
    間に密着状に配設した絶縁層２３ｄとから成る二
    層構造に形成したことを特徴とする多層プリント
    配線板。
JP1985176877U 1985-11-19 1985-11-19 Pending JPS6284973U (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP1985176877U JPS6284973U (ja) 1985-11-19 1985-11-19
US06/929,819 US4692843A (en) 1985-11-19 1986-11-13 Multilayer printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985176877U JPS6284973U (ja) 1985-11-19 1985-11-19

Publications (1)

Publication Number Publication Date
JPS6284973U true JPS6284973U (ja) 1987-05-30

Family

ID=16021337

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985176877U Pending JPS6284973U (ja) 1985-11-19 1985-11-19

Country Status (2)

Country Link
US (1) US4692843A (ja)
JP (1) JPS6284973U (ja)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5170931A (en) * 1987-03-11 1992-12-15 International Business Machines Corporation Method and apparatus for mounting a flexible film semiconductor chip carrier on a circuitized substrate
US5159535A (en) * 1987-03-11 1992-10-27 International Business Machines Corporation Method and apparatus for mounting a flexible film semiconductor chip carrier on a circuitized substrate
US4788767A (en) * 1987-03-11 1988-12-06 International Business Machines Corporation Method for mounting a flexible film semiconductor chip carrier on a circuitized substrate
JP2573016B2 (ja) * 1988-02-27 1997-01-16 アンプ インコーポレーテッド マイクロ入出力ピンおよびその製造方法
US5031308A (en) * 1988-12-29 1991-07-16 Japan Radio Co., Ltd. Method of manufacturing multilayered printed-wiring-board
JP2510747B2 (ja) * 1990-02-26 1996-06-26 株式会社日立製作所 実装基板
US5401913A (en) * 1993-06-08 1995-03-28 Minnesota Mining And Manufacturing Company Electrical interconnections between adjacent circuit board layers of a multi-layer circuit board
US5773195A (en) * 1994-12-01 1998-06-30 International Business Machines Corporation Cap providing flat surface for DCA and solder ball attach and for sealing plated through holes, multi-layer electronic structures including the cap, and a process of forming the cap and for forming multi-layer electronic structures including the cap
RU2134466C1 (ru) 1998-12-08 1999-08-10 Таран Александр Иванович Носитель кристалла ис
JP3288654B2 (ja) * 1999-07-23 2002-06-04 ヒロセ電機株式会社 電気コネクタの製造方法
JP3874062B2 (ja) * 2000-09-05 2007-01-31 セイコーエプソン株式会社 半導体装置
US6495771B2 (en) 2001-03-29 2002-12-17 International Business Machines Corporation Compliant multi-layered circuit board for PBGA applications
US7754976B2 (en) * 2002-04-15 2010-07-13 Hamilton Sundstrand Corporation Compact circuit carrier package
US8497203B2 (en) 2010-08-13 2013-07-30 International Business Machines Corporation Semiconductor structures and methods of manufacture
TWM441292U (en) * 2012-06-08 2012-11-11 Hon Hai Prec Ind Co Ltd Printed circuit board
US9007776B2 (en) * 2012-12-14 2015-04-14 Htc Corporation Electronic module

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1280356B (de) * 1965-09-16 1968-10-17 Telefunken Patent Mikrominiaturisierte Schaltungsanordnung und Verfahren zu ihrer Herstellung
US3537136A (en) * 1967-12-06 1970-11-03 Prvni Brnenska Strojirna Apparatus for briquetting metal chips
US3591839A (en) * 1969-08-27 1971-07-06 Siliconix Inc Micro-electronic circuit with novel hermetic sealing structure and method of manufacture
US3616532A (en) * 1970-02-02 1971-11-02 Sperry Rand Corp Multilayer printed circuit electrical interconnection device
US3829601A (en) * 1971-10-14 1974-08-13 Ibm Interlayer interconnection technique
US3936930A (en) * 1972-07-10 1976-02-10 Rca Corporation Method of making electrical connections for liquid crystal cells
US3904934A (en) * 1973-03-26 1975-09-09 Massachusetts Inst Technology Interconnection of planar electronic structures
CA1073557A (en) * 1976-06-30 1980-03-11 Ven Y. Doo Multilayer interconnect system, and method of making
US4225900A (en) * 1978-10-25 1980-09-30 Raytheon Company Integrated circuit device package interconnect means
US4216350A (en) * 1978-11-01 1980-08-05 Burroughs Corporation Multiple solder pre-form with non-fusible web
JPS55156395A (en) * 1979-05-24 1980-12-05 Fujitsu Ltd Method of fabricating hollow multilayer printed board
US4394712A (en) * 1981-03-18 1983-07-19 General Electric Company Alignment-enhancing feed-through conductors for stackable silicon-on-sapphire wafers
US4545610A (en) * 1983-11-25 1985-10-08 International Business Machines Corporation Method for forming elongated solder connections between a semiconductor device and a supporting substrate
US4581680A (en) * 1984-12-31 1986-04-08 Gte Communication Systems Corporation Chip carrier mounting arrangement
US4642889A (en) * 1985-04-29 1987-02-17 Amp Incorporated Compliant interconnection and method therefor

Also Published As

Publication number Publication date
US4692843A (en) 1987-09-08

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