JPH01167043U - - Google Patents

Info

Publication number
JPH01167043U
JPH01167043U JP1988063554U JP6355488U JPH01167043U JP H01167043 U JPH01167043 U JP H01167043U JP 1988063554 U JP1988063554 U JP 1988063554U JP 6355488 U JP6355488 U JP 6355488U JP H01167043 U JPH01167043 U JP H01167043U
Authority
JP
Japan
Prior art keywords
conductor
integrated circuit
hybrid integrated
dam
circuit according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1988063554U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988063554U priority Critical patent/JPH01167043U/ja
Publication of JPH01167043U publication Critical patent/JPH01167043U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10152Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/10175Flow barriers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Description

【図面の簡単な説明】
第1図は本考案の実施例を示す斜視図、第2図
A乃至Bは第1図の製方を説明する斜視図、第3
図は他の製方を示す斜視図、第4図は従来例を示
す図である。 1……絶縁基板、2……導体、3……半導体チ
ツプ、4……接合パツド、5……せき止め部、6
……バンプ電極。

Claims (1)

  1. 【実用新案登録請求の範囲】 (1) 絶縁基板上に導体を介して少なくともバン
    プ電極を有する半導体チツプが固着された混成集
    積回路において、前記半導体チツプが固着される
    前記導体の接合パツド近傍に前記接合パツド面よ
    り突出したせき止め部が設けられたことを特徴と
    する混成集積回路の導体構造。 (2) 前記せき止め部は前記導体と同一材料で形
    成されたことを特徴とする請求項1記載の混成集
    積回路の導体構造。 (3) 前記せき止め部を延在せしめ、前記せき止
    め部の一部分を他の半導体素子の接合パツドに用
    いることを特徴とする請求項1記載の混成集積回
    路の導体構造。 (4) 前記せき止め部はメツキあるいは蝕刻によ
    つて形成されたことを特徴とする請求項1記載の
    混成集積回路の導体構造。 (5) 前記絶縁基板はセラミツクスあるいは絶縁
    処理された金属基板を用いることを特徴とする請
    求項1記載の混成集積回路の導体構造。
JP1988063554U 1988-05-13 1988-05-13 Pending JPH01167043U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988063554U JPH01167043U (ja) 1988-05-13 1988-05-13

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988063554U JPH01167043U (ja) 1988-05-13 1988-05-13

Publications (1)

Publication Number Publication Date
JPH01167043U true JPH01167043U (ja) 1989-11-22

Family

ID=31289049

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988063554U Pending JPH01167043U (ja) 1988-05-13 1988-05-13

Country Status (1)

Country Link
JP (1) JPH01167043U (ja)

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