JPH01161526A - フレームメモリ制御方法 - Google Patents

フレームメモリ制御方法

Info

Publication number
JPH01161526A
JPH01161526A JP62320563A JP32056387A JPH01161526A JP H01161526 A JPH01161526 A JP H01161526A JP 62320563 A JP62320563 A JP 62320563A JP 32056387 A JP32056387 A JP 32056387A JP H01161526 A JPH01161526 A JP H01161526A
Authority
JP
Japan
Prior art keywords
frame
signal
frame memory
monitor
recording
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62320563A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0437453B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html
Inventor
Tadashi Yatsuno
八野　正
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu General Ltd
Original Assignee
Fujitsu General Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu General Ltd filed Critical Fujitsu General Ltd
Priority to JP62320563A priority Critical patent/JPH01161526A/ja
Publication of JPH01161526A publication Critical patent/JPH01161526A/ja
Publication of JPH0437453B2 publication Critical patent/JPH0437453B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Controls And Circuits For Display Device (AREA)
  • Dot-Matrix Printers And Others (AREA)
  • Digital Computer Display Output (AREA)
JP62320563A 1987-12-18 1987-12-18 フレームメモリ制御方法 Granted JPH01161526A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62320563A JPH01161526A (ja) 1987-12-18 1987-12-18 フレームメモリ制御方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62320563A JPH01161526A (ja) 1987-12-18 1987-12-18 フレームメモリ制御方法

Publications (2)

Publication Number Publication Date
JPH01161526A true JPH01161526A (ja) 1989-06-26
JPH0437453B2 JPH0437453B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1992-06-19

Family

ID=18122828

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62320563A Granted JPH01161526A (ja) 1987-12-18 1987-12-18 フレームメモリ制御方法

Country Status (1)

Country Link
JP (1) JPH01161526A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5727116A (en) * 1992-06-09 1998-03-10 Asahi Kogaku Kogyo Kabushiki Kaisha Image signal recording device with divided signal frame

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5727116A (en) * 1992-06-09 1998-03-10 Asahi Kogaku Kogyo Kabushiki Kaisha Image signal recording device with divided signal frame

Also Published As

Publication number Publication date
JPH0437453B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1992-06-19

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