JPH01157566A - Manufacture of cmos - Google Patents

Abstract

PURPOSE:$/To provide high breakdown strength by carrying out formation of a low density layer region of a source drain of a channel transistor and impurity implantation to a channel stopper region of the other channel transistor at the same time and by forming a selective oxide film in the region to oppose a gate electrode to the low density layer region with a thick oxide film between. CONSTITUTION:After a P well 12 is formed on an N substrate 11, an oxide film 13 is eliminat ed and a thin oxide film 14 is formed on the surface thereof and a nitride film 15, on the oxide film 14. Then the nitride film excepting a high density layer of each gate region and each source drain is eliminated by etching. Areas excepting regions 16a1, 17a1, 16a2, 17a2 and a region 18b within a P well 12 are covered with resist and N-type impurity is implanted. Similarly, areas excepting regions 16b1, 17b1, 16b2, 17b2, and a region 18a of a P channel transistor are covered with resist and P-type impurity is implanted. Successively, an oxide film 19 is formed using the nitride film 15 as a mask and the nitride film 15 and the oxide film 14 are eliminated to form an oxide film 20. N-type impurity is introduced into a polysilicon layer 21 formed on the surface, and a gate electrode pattern is formed to form high density layer regions 17a1, 17a2, 17b1, 17'2 through ion implantation. An insulation film 22 is formed and then holed. Al 23 is evaporated and an electrode wiring is formed thereafter. In this way, CMOS which operates at a very fast speed at high breakdown strength can be manufactured at a low costs.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention relates to a high breakdown voltage CMO in which a source region and a drain region are composed of a high concentration layer and a low concentration layer surrounding the high concentration layer.
The present invention relates to a method for producing S.

[Conventional technology]

In a MOS transistor, the source region and the drain region may have a two-layer structure consisting of a high concentration layer and a low concentration layer surrounding the high concentration layer in order to increase the breakdown voltage.

FIG. 2 shows the structure of an example of a conventional MO8) transistor of this type.

In the figure, 1 is the substrate, 2 is the drain low concentration layer region, and 3 is the substrate.
4 is a high concentration layer region of the drain, 4 is a channel stopper region, 5 is a gate oxide film, and 6 is a gate electrode.

If the drain side has a two-layer structure, the purpose of increasing the withstand voltage can be achieved, but the source side is usually also made to have a two-layer structure.

In the conventional manufacturing of MOS transistors with this type of structure,
The low concentration layer region 2 of the source/drain is formed in a shape surrounding the high concentration layer region 3 using a special mask. Furthermore, the gate electrode 6 is formed in a shape that covers the low concentration layer region 2 so that the surface of the low concentration layer region 20 is not reversed due to accumulation of charges.

[Problem that the invention seeks to solve]

In the conventional manufacturing of high-voltage CMOS with this type of structure, compared to the case of CMOS with a normal structure, each of the reservoirs forming the low concentration layer regions of the source and drain on the N-channel transistor side and the P-channel transistor side is dedicated. There is a problem in that the number of photolithography steps using masks increases, which directly leads to an increase in costs.

Furthermore, since the gate electrode 6 faces the low concentration layer region 2 with the thin oxide film 5 interposed therebetween, there is a problem in that the gate capacitance and the gate-drain capacitance increase significantly, resulting in a reduction in operation speed.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a method for manufacturing a high-voltage CMOS that can be manufactured in the same manufacturing process as a CMOS of a normal structure and that does not increase gate capacitance or gate-drain capacitance. With the goal.

[Means for solving problems]

In order to solve the above-mentioned conventional problems, this invention uses a method of using polysilicon for the gate electrode, and forms low concentration layer regions of the source and drain of each channel transistor. In this method, impurities are implanted into the stopper region simultaneously, a selective oxide film is formed in the region, and the gate electrode is placed opposite the low concentration layer region with the thick oxide film in between.

[Embodiments of the invention]

The manufacturing method of this invention will be explained below with reference to FIG.

A P well 12 is formed on an N substrate 11 [Figure (a)].

The oxide film (Si02) 13 used during well formation is removed, and a thin oxide film (Si02) 14 (100 to 400X
) and a nitride film (Si3N4) 15 on this oxide film 14.
(60()"1200X) [Figure (B)]. The nitride film other than the high concentration layer of each gate region and each source/drain is removed by etching [Figure (C)].

Next, the source/drain high/low concentration regions 16al, 17al, 16a2, 17a2 and P
The area other than the channel stopper region 18b of the channel transistor is covered with a 7-hole resist, and N-type impurities are implanted. In this case, the thickness of the photoresist and the implantation energy are set so that the impurity is implanted through the insulating film into the region where Si3N415 and 5i0214 overlap and is blocked by the photoresist [Figure (d)]. Similarly, the high and low concentration regions 16b of the source and drain of the P-channel transistor.

17b1, 16b2, 17b2 and the channel strami 4 region 18a in the P well 12 are covered with a 7 photoresist and P type impurities are implanted [Figure (e)].

Subsequently, selective ablation is performed using the nitride film 15 as a mask, and a thick oxide film 19 (0.8 to 1
．． 611m) [Figure (f)]. The nitride film 15 and the thin oxide film 14 thereunder are removed to form a gate oxide film 20 [FIG. (2)]. When the gate oxide film 20 has a breakdown voltage of 50V, an appropriate thickness is 700 to 2000X.

A polysilicon layer 21 is formed on the surface, and N-type impurities are introduced into this polysilicon layer 21 (this may be introduced at the time of forming the polysilicon layer 21), and unnecessary polysilicon is removed by etching to form the source and drain regions. Low concentration layer area], 6
Selective oxide film 1 on a1, 16a2.16b1°16b2
Form a gate electrode pattern covering 9 parts [Figure (h)
]. Using this gate electrode/turn 21 as a mask, ion implantation is performed to form the source/drain high concentration layer region 17a.
1+ '7a2+17b1, 17b2 [Figure (
1)].

The intermediate insulating film 22 is formed using, for example, P.
SG, BPSG, Si3N4, etc. are suitable), contact holes are opened in predetermined areas, Al is deposited on the entire surface, and unnecessary areas are removed by etching to form electrode wiring [Figure (j)] , When the formation of each part above is completed, the entire surface /? A passivation film is formed, and the passivation film on the bonding pad portion is removed.

The above description has been made regarding the case of forming 0MO8 on the N substrate 11, but the procedure is the same when forming on the P substrate, only the P type and N type are replaced.

According to the above method, a polysilicon type C with a normal structure
It can be manufactured in the same process as MO3, the cost increase of making the source/drain region into a two-layer structure is small, and the gate capacitance and gate-drain capacitance do not increase, which will hinder high-speed operation. There is no.

〔Effect of the invention〕

According to this invention, a high voltage 0MO8 having a two-layer structure in the source/drain region can be manufactured in the same process as the manufacturing process for an 0MO8 having a normal structure, so the cost increase due to the two-layer structure is small, and Since the gate capacitance can be reduced, an OMO8 with high breakdown voltage and high speed operation can be obtained at low cost.

[Brief explanation of the drawing]

FIG. 1 is a schematic sectional view for explaining the method of the present invention, and FIG. 2 is a schematic sectional view showing the structure of an example of a conventional MOS transistor of this type. 11...N substrate, 12...P well, 13 ・5i02
．． 14-5i02.15-Si3N4.16al,
16a2. ], 6b, , 16b2-low concentration layer, 17a1.1
7a2.17b1. 17b2 High concentration layer, 18a, 18b・Channel stopper region, 19...Selective oxide film, 20...Gate oxide film,
21 ・Polysilicon type, 22 ・Intermediate insulating film, 23...
Al, l, 14v, 14v, 410,000V, 1 town, 1 sword, τ ding ding. Patent applicant: New Japan Radio Co., Ltd.

Claims (1)

[Claims] In a method for manufacturing a high-voltage CMOS in which the source region and the drain region are composed of a high concentration layer and a low concentration layer surrounding the high concentration layer, a P-well (N-well) is formed on an N-type substrate (or a P-type substrate). Step, removing the oxide film during well formation and forming a thin oxide film on the surface and a nitride film on the oxide film, removing the nitride film in areas other than the gate region and the high concentration layer region of the source/drain by etching The source/drain height in the P-well (or N-well) is
A step of covering the region other than the low concentration layer region and the channel stopper region of the P channel transistor (N channel transistor) with a photoresist, and implanting N type (P type) impurities into the above region. Covering areas other than the high and low concentration layer regions of the drain and the channel stopper region of the P well (N well) with photoresist, implanting P type (N type) impurities into the above regions, and forming a selective oxide film using the nitride film as a mask. A process of removing the nitride film and a thin oxide film under the nitride film to form a gate oxide film, forming a polysilicon layer on the surface, and introducing N-type impurities into the polysilicon layer to remove unnecessary polysilicon. Step of removing the layer to form a gate electrode pattern that covers the selective oxide film portion on the low concentration layer region of the source and drain, and removing the high concentration layer region of each source and drain by ion implantation using the gate electrode pattern as a mask. A method for manufacturing a CMOS, comprising the steps of forming an intermediate insulating film, forming a contact hole and depositing Al to form an electrode wiring, and covering the surface with a passivation film.