JPH0793362B2 - Method of manufacturing CMOS - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method of manufacturing a high breakdown voltage CMOS in which a source region and a drain region have a high concentration and a low concentration layer surrounding the high concentration layer. .

[Conventional technology]

In order to increase the breakdown voltage of a MOS transistor, the source region and the drain region may have a two-layer structure including a high concentration layer and a low concentration layer surrounding the high concentration layer.

FIG. 2 shows an example of the structure of a conventional MOS transistor of this type.

In the figure, 1 is a substrate, 2 is a low concentration layer region of the drain, 3
Is a drain high-concentration layer region, 4 is a channel stopper region, 5 is a gate oxide film, and 6 is a gate electrode.

If the drain side has a two-layer structure, the purpose of increasing the breakdown voltage can be achieved, but normally, the source side also has a two-layer structure.

In the conventional manufacture of this type of structure MOS transistor, the low-concentration layer regions 2 of the source / drain are formed in a shape surrounding the high-concentration layer region 3 by using a dedicated mask. Further, the gate electrode 6 is formed in a shape covering the low concentration layer region 2 so that the surface of the low concentration layer region 2 is not inverted due to the accumulation of charges.

[Problems to be solved by the invention]

In the conventional manufacturing of a high breakdown voltage CMOS of this type structure, compared with the case of a normal structure CMOS, the N-channel transistor side and the P
There is a problem in that the number of photolithography processes using dedicated masks for forming the source / drain low-concentration layer regions on the channel transistor side increases, which directly leads to an increase in cost.

Further, since the gate electrode 6 faces the low-concentration layer region 2 across the thin oxide film 5, there is a problem that the operation speed is reduced due to a large increase in the gate capacitance and the gate / drain capacitance.

The present invention has been made to solve the above problems, and can be manufactured by the same manufacturing process as a CMOS having a normal structure, and has a high withstand voltage CM that does not increase the gate capacitance and the gate / drain capacitance.
The purpose is to provide a method of manufacturing an OS.

[Means for solving problems]

In order to solve the above-mentioned conventional problems, the present invention is based on a method of using polysilicon for the gate electrode, and the formation of the low concentration layer regions of the source / drain of each channel transistor is carried out by the channel of another channel transistor. This method is carried out at the same time as the implantation of impurities into the stopper region, and at the same time, a selective oxide film is formed in the region, and a thick oxide film is sandwiched between the gate electrode and the low concentration layer region.

Example of Invention

 The manufacturing method of the present invention will be described below with reference to FIG.

A P well 12 is formed on the N substrate 11 [FIG. The oxide film (SiO ₂ ) 13 at the time of forming the well is removed, and a thin oxide film (SiO ₂ ) 14 (100 to 400 Å) is formed on the surface, and a nitride film (Si ₃ N ₄ ) 15 ( 600-1200Å) is formed [Fig. (B)]. The nitride film other than the high-concentration layer in each gate region and each source / drain is removed by etching [FIG. (C)].

Next, the source / drain high / low concentration regions 16a ₁ , 17a ₁ , 16a ₂ , 17a ₂ in the P-well 12 and the channel stopper region 18b of the P-channel transistor are covered with a photoresist N.
Drive in mold impurities. In this case, the impurities are Si ₃ N ₄ 15 and S
The thickness of the photoresist and the implantation energy are set so that the region where iO ₂ 14 overlaps is implanted through the insulating film and blocked by the photoresist [FIG. (d)]. Similarly, the high / low concentration regions 16b ₁ , 17b ₁ , 16b ₂ , 17b ₂ of the source / drain of the P-channel transistor and the channel stopper region 18a in the P-well 12 are covered with a photoresist P.
The impurities of the mold are implanted [Fig. (E)].

Then, selective oxidation is performed using the nitride film 15 as a mask,
Thick oxide film 19 (0.8-1.6 μm) on the part not covered with
Are formed [Fig. (F)]. The nitride film 15 and the thin oxide film 14 underneath are removed to form a gate oxide film 20 [FIG. (G)].
The gate oxide film 20 is properly 700 to 2000 Å when the withstand voltage is 50V.

A polysilicon layer 21 is formed on the surface, and this polysilicon layer 21
N-type impurities are introduced into 21 (may be introduced at the time of forming the polysilicon layer 21), and unnecessary polysilicon is removed by etching to form the low concentration regions 16a ₁ , 16a ₂ , 16 of the source / drain.
A gate electrode pattern is formed to cover the selective oxide film 19 portions on b ₁ and 16b ₂ [FIG. (h)]. This gate electrode pattern 21
Using the mask as a mask, high concentration layer regions 17a ₁ , 17a ₂ , 17b ₁ and 17b ₂ of the source / drain are formed by ion implantation or the like [FIG. (I)].

An intermediate insulating film 22 is formed (for example, PSG, BP
(SG, Si ₃ N ₄ etc. are suitable), a contact hole is opened in a predetermined portion, Al is vapor-deposited on the entire surface, and an unnecessary portion is removed by etching to form an electrode wiring [Fig. (J)]. ]. When the formation of each of the above parts is completed, a passivation film is formed on the entire surface, and the passivation film in the bonding pad part is removed.

The above description is for the case where the CMOS is formed on the N substrate 11, but the procedure is the same when the CMOS is formed on the P substrate, except that the P type and the N type are interchanged.

According to the above method, the normal structure polysilicon type CM
It can be manufactured in the same process as the OS manufacturing process, the cost increase for making the source / drain region into a two-layer structure is small, and the gate capacitance and gate / drain capacitance do not increase, which hinders high-speed operation. There is no.

〔The invention's effect〕

According to this invention, a high breakdown voltage CMOS having a double-layer source / drain region can be manufactured in the same process as the manufacturing process of a CMOS having a normal structure, so that the cost increase for forming a double-layer structure is small, and Since the gate capacitance can be reduced, a high breakdown voltage and high speed CMOS can be obtained at low cost.

[Brief description of drawings]

FIG. 1 is a schematic sectional view for explaining the manufacturing method of the present invention, and FIG. 2 is a schematic sectional view showing the structure of an example of a conventional MOS transistor of this type. 11 …… N substrate, 12 …… P well, 13 …… SiO ₂ , 14 …… Si
O ₂ , 15 …… Si ₃ N ₄ , 16a ₁ , 16a ₂ , 16b ₁ , 16b ₂ …… Low concentration layer,
17a ₁ , 17a ₂ , 17b ₁ , 17b ₂ ...... High concentration layer, 18a, 18b ...... Channel stopper region, 19 ...... Selective oxide film, 20 ...... Gate oxide film, 21 ...... Polysilicon layer, 22 ...... Intermediate insulating film, 23 ……
Al, the same reference numerals in the respective drawings indicate the same parts.

Claims (1)

[Claims] 1. A method of manufacturing a high breakdown voltage CMOS, wherein a source region and a drain region are composed of a high-concentration layer and a low-concentration layer surrounding the high-concentration layer, and a P-type substrate is formed on the N-type substrate (or P-type substrate).
Step of forming well (N well), step of removing oxide film at the time of forming well and forming thin oxide film on the surface and nitride film on the oxide film, high concentration layer area of gate region and source / drain Other than the nitride film by etching, the source / drain high / low concentration layer regions in the P well (or N well) and the P channel transistor (N
A step of covering the region other than the channel stopper region of the channel transistor) with a photoresist and implanting an N-type (P-type) impurity in the region.
The regions other than the high / low concentration layer regions of the source / drain of the channel transistor) and the channel stopper region of the P well (N well) are covered with photoresist, and P-type (N
Type) impurities, a step of forming a selective oxide film using the nitride film as a mask, a step of removing the nitride film and a thin oxide film under the nitride film to form a gate oxide film, and a polysilicon layer on the surface. Forming a gate electrode pattern covering the selective oxide film portion on the low concentration layer regions of the source / drain by forming an N type impurity in the polysilicon layer and removing the unnecessary polysilicon layer; A step of forming a high concentration layer region of each source / drain by ion implantation or the like using a pattern as a mask; a step of forming a contact hole in which an intermediate insulating film is formed and depositing Al to form an electrode wiring;
A method for manufacturing a CMOS, comprising a step of covering the surface with a passivation film.