JPH0372677A - Manufacture of read only memory device - Google Patents

Abstract

PURPOSE:To reduce turnaround time, and prevent the alignment deviation of a mask, by forming a metal wiring layer so as to evade the channel region of an MIS transistor on a substrate, and selectively introducing impurity into the channel region by using the metal wiring layer as a part of a mask. CONSTITUTION:An aluminum system wiring layer 9 is formed on an interlayer insulating film 8 so as not to overlap with a channel region 7 on a plane and to evade it. Next, a resist film 13 is comparatively thickly formed, which is selectively exposed and developed to form a resist mask. An aperture is formed in the resist film 13 at a part corresponding with the channel region 7 of an MOS transistor to be turned into a depletion type. Since the aluminum system wiring layer 9 functions as a part of a mask in a region A1, high resolution is not required for the pattern of the resist mask 13. By using the resist film 13 wherein only the part transforming the MOS transistor into a depletion type is opened, high energy ion is implanted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a NAND type read-only memory device in which MIS (MIS) transistors are connected in series.

[Summary of the invention]

The present invention is a method for manufacturing a NAND type read-only memory device configured by connecting MISI transistors in series, in which a metal wiring layer avoiding the channel region of an MIS transistor is used as a part of a mask to selectively impurity. After introducing impurities or selectively introducing impurities between a plurality of parallel first gates, a second gate is formed between the first gates, and for forming the second gate. By using the patterning mask as part of the mask for selective ion implantation under the first gate, the turn-around time and number of steps in the manufacture of read-only memory devices can be shortened. be.

[Prior Art] As read-only memory devices, particularly mask ROMs, become more highly integrated, the NAND type has become mainstream.

This NAND type mask ROM has a memory cell structure in which a plurality of MO3L transistors are arranged in series. For example, an enhancement (normally off) type MOS transistor is replaced with a depletion (normally on) type MOS transistor.
Information is programmed (written) by changing to an S transistor.

FIG. 7 is a sectional view of a memory cell of a mask ROM having a multi-gate structure, and FIG. 8 is an equivalent circuit diagram thereof.

To briefly explain this multi-gate structure mask ROM with reference to FIG.
A plurality of gates are formed in parallel, and a second gate 103 is formed between the first gates 102 with an insulating film interposed therebetween using a second Nth wiring layer. Impurities are selectively implanted into the lower part of the first gate 102 and the lower part of the second gate 103, and the MOS transistor having the impurity diffusion region 104 into which the impurity is implanted is made into a depletion type.

Reading is performed by applying a gate voltage of, for example, 0. If the selected MO3I-ranjisku is an enhancement type, the potential of the bit line is high, and if it is a depletion type, the potential of the bit line is high. be brought to a low level.

[The problem that the invention aims to solve]

Generally, in memory devices such as the above-mentioned mask ROM that are programmed and shipped as products, it is required to shorten the turnaround time from ordering the program code to completing the product. However, in conventional read-only memory devices, programming is performed by ion implantation before forming the gate electrode, which requires a long process.

Furthermore, although a mask ROM with a multi-gate structure as shown in FIG. 7 has the advantage of being highly integrated, it suffers from problems such as mask misalignment during ion implantation for programming and the spread of impurity diffusion regions between adjacent gates. This problem has made it difficult to increase the degree of integration, and increasing the degree of integration requires an increase in the number of steps, such as removing a portion of the substrate to compensate for positional deviations.

Therefore, in view of the above-mentioned technical problems, the present invention aims to provide a method for manufacturing a read-only memory device that shortens the turn-around time while simplifying the steps necessary for high integration. The first object is to provide a method for manufacturing a read-only memory device that reduces the number of steps and prevents misalignment of masks and the like.

[Means to solve the problem]

A method for manufacturing a read-only memory device according to the first invention of the present application for achieving the first object described above is a method for manufacturing a NAND-type read-only memory device configured by connecting MIS transistors in series. Then, the above M on the substrate
A metal wiring layer is formed avoiding the channel region of the IS transistor, and programming is performed by selectively introducing impurities into the channel region using the metal wiring layer as part of a mask. The metal wiring layer formed avoiding the channel region has a pattern that cannot be formed on a plane, and can be formed of, for example, an aluminium-based wiring layer.

When programming, a resist mask can be used together with the metal wiring layer, and impurities can be introduced by penetrating the gate by ion implantation.

Further, the method for manufacturing a read-only memory device according to the second invention of the present application for achieving the second objective is a method for manufacturing a NAND-type read-only memory device configured by connecting MIS transistors in series. a process of forming a plurality of first gates in parallel on a substrate; a process of selectively introducing impurities into the substrate surface between the first gates using the first gates as part of a mask; and patterning. a step of forming a plurality of second gates in parallel with the first gate with an insulating film interposed between the first gates using a patterning mask; The method is characterized in that it includes a step of selectively implanting impurities into the substrate surface under the first gate.

[Effect]

In the method for manufacturing a read-only memory device according to the first invention of the present application, since the metal wiring layer is formed avoiding the channel region of the MIS transistor, programming by ion implantation or the like can be performed after forming the metal wiring layer. Further, since the metal wiring layer formed in a pattern that avoids the channel region is used as it is as part of the mask, problems such as mask displacement are alleviated.

Further, in the method for manufacturing a read-only memory device according to the second invention of the present application, the first gate is used as a part of a mask for programming the MIS transistor of the second gate, and the patterning mask is used as a part of the mask for programming the MIS transistor of the second gate. It is used as part of the mask for MIS transistors. Therefore, programming is performed in a self-aligned manner, and problems such as mask misalignment are also solved.

〔Example] Preferred embodiments of the present invention will be described with reference to the drawings.

First Embodiment This embodiment is an example of a method for manufacturing a mask ROM, and the mask ROM has a structure in which an aluminum-based wiring layer, which is a metal wiring layer, is wired on an element isolation region.

First, FIG. 4 shows the circuit configuration of a memory cell of a mask ROM manufactured according to this embodiment. In its circuit configuration, two series-connected MOS transistors are arranged between the bit line BL and the ground voltage line. Two rows on the bit line BL side are MOS transistors for bit selection, and one of the two columns is alternatively selected by selection lines BS1 and BS2. The other MOS transistors are transistors for storing information, and their gates have a configuration in which a plurality of word lines W1 to W8 are arranged in parallel. MOS transistors having such word lines W1 to W8 as gate electrodes are selectively formed into an enhancement type and a depletion type by ion implantation as described later, and are programmed.

Next, the structure of the mask ROM before being programmed will be described with reference to FIGS. 1 to 3.

A gate insulating film 2 is formed on a semiconductor substrate 1, and on the gate insulating film 2, selection lines BSI,
BS2 and word lines W1 to W8 are formed. These selection lines BSI, BS2 and word lines W1 to W8 are made of a material such as polysilicon, and have side walls 3 on the sides.
are formed respectively. These selection lines BSI, BS
2 and word lines W1 to W8 extend with the X direction in FIG.
BS2 and word lines W1 to W8 are formed so as to cross over the element isolation region 4, as shown in FIG. The element isolation region 4 is formed along the rows of MO3I transistors with the Y direction in FIG. 1 as the longitudinal direction, and electrically isolates the MO3I transistor rows. A channel stopper region 12 is formed under the element isolation region 4.

A source train region is formed on the surface of the semiconductor substrate 1 between each selection line BSI, BS2 and word lines W1 to W8. This source/drain region is formed into a so-called LDD structure consisting of a high concentration impurity region 5 and a low concentration impurity region 6 by utilizing the offset caused by the sidewall 3. High concentration impurity regions 5 at both ends of the MOS transistor array are connected to a bit line via a contact hole 14 or to a ground voltage line for supplying ground voltage GND. The surface of the semiconductor substrate 1 under each of the selection lines BSI, BS2 and the word lines W1 to W8 between these source/drain regions is a channel region 7.

Then, as described later, impurity ions are selectively implanted into these channel regions 7 to obtain enhancement type and depletion type MOS transistors.

Such selection lines BSI, BS2 and word lines W1 to W
An interlayer insulating film 8 is formed over the entire surface of the interlayer insulating film 8, and an aluminum wiring layer 9 functioning as a bit line is formed on the interlayer insulating film 8. This aluminum wiring layer 9 extends with the Y direction in FIG. 1 as the longitudinal direction,
MOS transistor 1 is formed avoiding the channel region 7 of the transistor array. That is, the aluminum-based wiring layer 9 has a window 10 or a space 11 between the bisotho lines on the channel region 7, and the aluminum-based wiring layer 9 is not formed on the channel region 7. As shown in FIG. 1, this aluminum wiring layer 9 extends in the Y direction and is bent in the X direction at a selection line BS2 in order to connect to the high concentration impurity region 5 of the substrate 1 via a contact hole 14. It will be done.

From the pre-program state shown in FIGS. 1 to 3 as described above, the program is executed and the product is shipped. This will be explained with reference to FIGS. 5(a) and 5(b).

Figure 5(a) shows the state before programming, and the second
It has the same cross-sectional structure as the figure. In this pre-program state, an aluminum-based wiring layer 9 is formed on the interlayer insulating film 8, avoiding the channel region 7 in a planar manner. Therefore, the aluminum-based wiring layer 9 is formed so as to overlap the element isolation region 4 on a plane.

Second, as shown in FIG. 5(1), a relatively thick resist film 13 is formed, and this is selectively exposed and developed to obtain a resist mask. The thickness of the resist film 13 is such that even impurities implanted with high energy are prevented from permeating, and the resist film 13 has a thickness of, for example, about several μm. The resist film 13 is opened at a portion corresponding to the channel region 7 of the MOS transistor to be made into a depletion type MOS transistor.

The area to be made into an enhancement type is a thick resist film 13.
remains attached. The pattern of this resist film 13 does not need to have a high resolution because the aluminum wiring layer 9 functions as part of a mask in the region A. Therefore, the process can be simplified.

High-energy ion implantation is performed using a resist film 13 that is open only where the MOS transistor is to be made into a depletion type. The energy of this ion implantation is
For example, 1 m of impurity is implanted into the channel region 7 at a voltage of 800 to 2 MeV, penetrating the interlayer insulating film 8 and the selection line or word line in a region where the resist film 13 is not formed.

Due to this implanted impurity of 1 m, the dark value voltage V1. changes, the MOS transistor becomes a depletion type, and the mask ROM is programmed.

Note that impurities may be introduced in advance into the selection line portion.

After such a program, overcoat.

After forming pads, sintering, etc., the mask ROM is
complete. The subsequent steps of the program are significantly shorter than previous processes, resulting in reduced turnaround time.

As described above, in the mask ROM manufacturing method of this embodiment, after the aluminum-based wiring layer 9 is formed avoiding the area above the channel region 7, ion implantation for programming is performed. Therefore, the turn around time can be extremely short.

In addition, since the aluminum-based wiring layer 9 can be used as a part of the mask during ion implantation for programming,
A fine resist film is not required, which is advantageous when achieving high integration, and the process itself can be simplified.

Second Embodiment This embodiment is a method of manufacturing a mask ROM having a so-called multi-gate structure, and is an example in which a first gate and a patterning mask are used in the program. This embodiment will be described below with reference to FIGS. 6(a) to 6(d).

First, as shown in FIG. 6(a), a gate insulating film 22, an element isolation region (not shown), etc. are formed on a semiconductor substrate 21, and a first gate electrode layer 23 is formed on the gate insulating film 22. Ru. The first gate electrode layer 23 is formed, for example, by forming a polysilicon layer over the entire surface, and then etching it by an anisotropic etching method so as to form a plurality of parallel patterns.

After patterning the first gate electrode layer 23, a P2O layer containing phosphorus is formed over the entire surface, and the P2O layer is etched and hacked. By this etch hack, sidewalls 24 made of a P2O layer are formed on the sides of the first gate electrode layer 23. Subsequently, the first gate electrode layer 2 is heated by heat treatment.
An oxide film 25 is formed on the surface of the substrate between the sidewall 24 and the sidewall 24 made of a P2O layer.
Phosphorus is diffused from 4, and source/drain regions 26 of the MOS transistor array are formed in self-alignment with the sidewalls 24 from the diffusion of phosphorus.

Next, as shown in FIG. 6(b), a resist film 2 is applied to the entire surface.
7 is formed, and the resist film 27 is selectively exposed and developed. The pattern of this resist film 27 corresponds to the arrangement of the MOS transistors to be programmed, and a window 28 is formed in the region where ions are to be implanted.

The first gate electrode layer 23 covered with the oxide film 25 faces the bottom of the window 28 . That is, the pattern of the window portion 28 may be a bitter pattern since the first gate electrode layer 23 functions as a part of a mask for ion implantation. Therefore, it is possible to simplify the process, and it is also advantageous for increasing the degree of memory integration. Next, ion implantation is performed using the window portion 28. This ion injection 6 uses a second gate electrode layer 30, which will be described later, as a gate.
This is a program for the OS transistor, and the MOS transistor into which impurities are implanted is made into a depletion type.

Next, the resist film 27 is removed, and as shown in FIG. 6C, a polysilicon layer is deposited on the entire surface, and a resist film is formed to pattern this. The polysilicon layer is in contact with the substrate surface between the first gate electrode layers 23 with an insulating film 25 interposed therebetween. The resist film is selectively exposed and developed to form a patterning mask 29 in a pattern that covers the area between the plurality of first gate electrode layers 23 formed in parallel. Then, anisotropic etching is performed using the patterning mask 29 to pattern the polysilicon layer to obtain a second gate electrode layer 30. A plurality of second gate electrode layers 30 are formed in parallel between the first gate electrode layers 23 .

Next, as shown in FIG. 6(d), the patterning mask 29 used to form the second gate electrode layer 30 is left as it is without being removed, and a resist film 31 is further formed as a mask for programming. Form on the entire surface. This resist film 31 is formed relatively thick because the next ion implantation is a high energy ion implantation that penetrates the first gate electrode layer 23. Generally, when the mask ROM is formed thickly, the resolution is sacrificed, but in the manufacturing method of the mask ROM of this embodiment,
Patterning mask left unremoved 29. Since the second gate electrode 30 functions as part of a mask, the window portion 32 can be formed to have a larger size than the pattern of the channel region into which ions are to be implanted. Therefore,
It is possible to simplify the process, and it is also advantageous for increasing the degree of integration of the mask ROM.

After forming the resist film 31 having such a window portion 32,
Perform ion implantation for programming. This ion implantation is performed so that the impurity is implanted through the first gate electrode layer 23 and into the channel below it. In this way, programming of the MOS transistor using the first gate electrode layer 23 as the gate is performed 7 8 , and the MOS transistor into which the impurity has been implanted is made into a depletion type.

Thereafter, the resist film 31 and the like are removed, and necessary wiring and the like are formed according to a normal process, to complete the mask ROM.

In the method for manufacturing the mask ROM of this embodiment, which includes such steps, the resist films 27 and 31 formed during ion implantation for programming are formed by the first gate electrode layer 23 and the patterning mask 29, respectively. In order to function as a part of the mask, it can be selectively exposed to a larger size, which allows the process to be simplified and is also advantageous for higher integration of the mask ROM.

Further, since the patterning mask 29 is also used as a mask for forming the second gate electrode layer 30, ion implantation using the patterning mask 29 and formation of the second gate electrode layer 30 are performed as a result. This will be done on a self-aligned line, which is advantageous for high integration.

Further, in the method of manufacturing the mask ROM of this embodiment, nine source/drain regions 26 are formed using sidewalls 24 in alignment with the regions between fine gates. Therefore, it is advantageous for highly integrating the ROM of the mask, and problems such as misalignment of the mask and misalignment of the diffusion region can be solved.

(Effects of the Invention) In the method for manufacturing a read-only memory device according to the first invention of the present application, the metal wiring layer is formed avoiding the channel region,
Since impurities are introduced for programming using the metal wiring layer as part of a mask, turn-around time can be shortened, which simplifies the process and is also advantageous for high integration. It is.

Further, in the method for manufacturing a read-only memory device according to the second invention of the present application, since the first gate and the patterning mask are each used as a part of the mask, there is no need to form a resist film with a fine pattern. , it is possible to simplify the process, and it is advantageous for high integration. Further, the ion implantation using a patterning mask and the formation of the second gate are performed on a self-alignment line, which is advantageous for simplifying the process and miniaturizing the device.

[Brief explanation of drawings]

FIG. 1 is a partial plan view of an example of a read-only memory device according to the method of manufacturing a read-only memory device of the present invention, and FIG. 2 is a partial plan view of an example of the read-only memory device taken along the line ■-■ in FIG. 3 is a sectional view of an example of the read-only memory device taken along the line ■-■ in FIG.
The figure is a circuit diagram of a memory cell of an example of the above-mentioned read-only memory device, and FIGS. Each is a process sectional view. Figure 6 (
A) to FIG. 6D are process sectional views for explaining another example of the method for manufacturing a read-only memory device according to the present invention according to the steps. FIG. 7 is a schematic cross-sectional view of a conventional mask ROM having a so-called multi-gate structure, and FIG. 8 is a circuit diagram of a memory cell of the conventional mask ROM. 1...Semiconductor substrate 7...Channel region 8...Interlayer insulating film 9...Aluminum wiring layer 10...Window portion 11...Space 13...Resist film BSI BS2...Selection Lines W1 to W8...Word line 21...Semiconductor substrate 23...First gate electrode layer 24...Side wall 27...Resist film 29...Patterning mask 30...Second Gate electrode layer 31...resist film

Claims (2)

[Claims] (1) In a method of manufacturing a NAND type read-only memory device configured by connecting MIS transistors in series, a metal wiring layer is formed avoiding the channel region of the MIS transistor on the substrate, and the metal wiring layer is A method of manufacturing a read-only memory device, characterized in that programming is performed by selectively introducing impurities into the channel region as part of a mask. (2) A method for manufacturing a NAND type read-only memory device configured by connecting MIS transistors in series, including a step of forming a plurality of first gates in parallel on a substrate, and masking the first gates. A step of selectively introducing impurities into the substrate surface between the first gates as part of the process, and a step of introducing impurities into the substrate surface between the first gates using a patterning mask and inserting a plurality of second gates into the first gates with an insulating film interposed between the first gates. A read-only method comprising the steps of: forming the patterning mask in parallel with the gate; and selectively implanting impurities into the substrate surface below the first gate using the patterning mask as part of an ion implantation mask. A method for manufacturing a memory device.