JPH0115184Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in junction field effect transistors.

As shown in FIG. 1, a conventional junction field effect transistor includes source and drain regions 3 and 4 surrounded by a gate region 1 and sandwiching a channel region 2 below the gate region 1. Rectangular source and drain contact regions 5 and 6 were provided on surfaces 3 and 4 in parallel with the channel region 2.

In such a junction field effect transistor, the source and drain contact regions 5 and 6 are provided with the same length up to the ends, or corners, of the source and drain regions 3 and 4, and the busses to the gate region 1 are also provided with approximately the same length. It was designed to be.
However, although such a pattern does not cause any problems when used at a low voltage, it is completely unsuitable for a high voltage structure. That is, since the region between the drain and gate is used with a reverse bias, the electric field is concentrated at the end or corner of the drain contact region 6 of the drain region 4, resulting in avalanche breakdown.

The present invention has been made in view of this point, and one embodiment of the present invention will be described in detail with reference to FIGS. 2 and 3.

As shown in FIG. 2, the junction field effect transistor according to the present invention is provided with source and drain regions 13 and 14 surrounding a gate region 11 and sandwiching a channel region 12 below the gate region 11. , 14 are provided with rectangular source and drain contact regions 15 and 16, and the distance between the end, that is, the corner, of the drain contact region 16 and the gate region 11 is set from the part facing the channel region 12 and the bus a of the gate region 11. The bus b is also long so that the corner portion of the drain contact 16 and the gate region 11 are spaced apart from each other.

The present inventor proposed a junction field effect transistor in which the length of the gate region 11 is 3 μm, the specific resistance of the channel region under the gate region 11 is 8 Ωcm, and the specific resistance of the substrate serving as the lower gate is 30 Ωcm. The withstand voltage was measured by setting the bus a of the drain contact region 16 to 10 μm and varying the bus b at the end or corner portion of the drain contact region 16. As a result, the experimental results shown in FIG. 3 were obtained. As is clear from Figure 3, when bus b is smaller than bus a, the withstand voltage is greatly reduced.
For example, even if bus a and bus b are designed equally, the withstand voltage will be
I can only get 170V. In contrast, bus b
If designed to 150μm, the withstand voltage can be improved to 240V,
It can be seen that even if the bus b is made longer than that, the breakdown voltage does not improve.

As described in detail above, the present invention is advantageous in that the withstand voltage can be easily improved by simply lengthening the bus b to the gate region 11 at the end of the drain contact region 16 where electric fields tend to concentrate, that is, at the corner. be.

[Brief explanation of the drawing]

FIG. 1 is a top view illustrating a conventional example, FIG. 2 is a top view illustrating the present invention, and FIG. 3 is a characteristic diagram illustrating experimental results of the present invention. 11 is a gate region, 12 is a channel region, 1
3, 14 are source and drain regions, 15, 1
6 is a source and drain contact region.

Claims (1)

[Scope of utility model registration request] A junction field effect transistor comprising a source/drain region surrounded by a gate region and provided across a channel region below the gate region, and a rectangular source/drain contact region provided on the surface of the source/drain region. In the method, a distance between a short side of the drain contact region and the gate region is made larger than a distance between a long side of the drain contact region, which faces the channel region and the source contact region, and the gate region. A junction field effect transistor characterized by: