JPH0115150Y2 - - Google Patents
Info
- Publication number
- JPH0115150Y2 JPH0115150Y2 JP8475882U JP8475882U JPH0115150Y2 JP H0115150 Y2 JPH0115150 Y2 JP H0115150Y2 JP 8475882 U JP8475882 U JP 8475882U JP 8475882 U JP8475882 U JP 8475882U JP H0115150 Y2 JPH0115150 Y2 JP H0115150Y2
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- composite component
- substrate
- low
- capacitance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 claims description 57
- 239000000758 substrate Substances 0.000 claims description 23
- 239000002131 composite material Substances 0.000 claims description 20
- 238000010030 laminating Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 description 7
- 239000011521 glass Substances 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 5
- 238000000576 coating method Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 238000010304 firing Methods 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000003973 paint Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000003475 lamination Methods 0.000 description 1
Landscapes
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Description
【考案の詳細な説明】
本考案は複合部品に関し、特に混成集積回路基
板として有用なコンデンサ内蔵型の複合部品に関
する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a composite component, and particularly to a composite component with a built-in capacitor useful as a hybrid integrated circuit board.
複合部品の基板を例えば混成集積回路の基板と
して利用する場合には、コンデンサは内蔵型に形
成される。コンデンサ内蔵型の複合部品は、一般
には、誘電体層とコンデンサ電極用導電パターン
とを交互に積層し、焼成して一体化した積層コン
デンサより構成されている。各内蔵コンデンサの
電極の端部が積層体の端面に露出され、これら露
出電極端部に適当な導電ペイントを被着し、電極
引出端子を形成している。これら電極引出端子は
通常は積層体の対向する端面に形成されており、
従つて比較的大容量のコンデンサと小容量のコン
デンサの引出端子が積層体の同じ端面に引出さ
れ、引出端子の位置の設計が煩雑となる欠点があ
つた。 When the substrate of a composite component is used as a substrate of a hybrid integrated circuit, for example, the capacitor is formed as a built-in type. Composite parts with built-in capacitors are generally composed of a multilayer capacitor in which dielectric layers and conductive patterns for capacitor electrodes are alternately laminated and fired to integrate them. The ends of the electrodes of each built-in capacitor are exposed on the end face of the laminate, and a suitable conductive paint is applied to these exposed electrode ends to form electrode lead terminals. These electrode lead terminals are usually formed on opposite end surfaces of the laminate.
Therefore, the lead-out terminals of a relatively large-capacity capacitor and a small-capacity capacitor are drawn out to the same end face of the laminate, resulting in a drawback that the design of the position of the lead-out terminals becomes complicated.
本考案の上記欠点を除去するためになされたも
ので、小容量のコンデンサの引出端子と比較的大
容量のコンデンサの引出端子とを90゜角度の異な
る位置に形成した複合部品を提供するものであ
る。 This invention has been made to eliminate the above-mentioned drawbacks of the present invention, and provides a composite component in which the lead-out terminals of a small-capacity capacitor and the lead-out terminals of a relatively large-capacity capacitor are formed at different positions at 90° angles. be.
以下、本考案の一実施例につき、添付図面を参
照して詳細に説明する。 Hereinafter, one embodiment of the present invention will be described in detail with reference to the accompanying drawings.
第1図は低誘電率の誘電体を使用して任意の製
造方法、例えば誘電体層とコンデンサ電極用導電
パターンとを交互に積層する方法、により製造さ
れた低容量の3つのコンデンサC1〜C3を内蔵す
る第1のコンデンサ基板1を示す。このコンデン
サ基板1を製造するに当り、各内蔵コンデンサ
C1〜C3の電極端部CEを、図示するように、コン
デンサ基板1の例えば図において上下方向の対向
する端面に露出するようにする。また、図示する
ように、コンデンサ基板1の右下角部に方向性指
示マーク2を付けておく。勿論、方向性指示マー
ク2の位置は右下角部に限定されるものではな
い。 Figure 1 shows three low capacitance capacitors C 1 ~ manufactured using a dielectric material with a low dielectric constant by any manufacturing method, such as a method of alternately laminating dielectric layers and conductive patterns for capacitor electrodes. A first capacitor substrate 1 incorporating C 3 is shown. In manufacturing this capacitor board 1, each built-in capacitor
As shown in the figure, the electrode end portions C E of C 1 to C 3 are exposed to opposing end surfaces of the capacitor substrate 1, for example, in the vertical direction in the figure. Further, as shown in the figure, a direction indicator mark 2 is attached to the lower right corner of the capacitor board 1. Of course, the position of the direction indicator mark 2 is not limited to the lower right corner.
第2図は高誘電率の誘電体を使用して任意の製
造方法、例えば上記した積層方法、により製造さ
れた比較的高容量の3つのコンデンサC4〜C6を
内蔵する第2のコンデンサ基板3を示す。この第
2のコンデンサ基板3を製造するに当り、各内蔵
コンデンサC4〜C6の電極端部CEは、図示するよ
うに、第1のコンデンサ基板1とは90度角度の異
なる図において左右方向の対向する端面に露出さ
せる。また、第1のコンデンサ基板1と同じ位置
に方向性指示マーク2を付けておく。第1および
第2のコンデンサ基板1および3は同じ形状、寸
法を有することはいうまでもない。 FIG. 2 shows a second capacitor board containing three relatively high capacitance capacitors C 4 to C 6 manufactured by any manufacturing method, such as the above-described lamination method, using a dielectric with a high permittivity. 3 is shown. In manufacturing this second capacitor board 3, the electrode ends C E of each of the built-in capacitors C 4 to C 6 are placed on the left and right sides in a view at a 90 degree angle from the first capacitor board 1, as shown in the figure. Expose on opposite end faces. Further, a direction indicating mark 2 is attached at the same position as the first capacitor board 1. It goes without saying that the first and second capacitor substrates 1 and 3 have the same shape and dimensions.
次に、第3図に示すように、第1および第2の
コンデンサ基板1および3と同じ形状、寸法の適
当な誘電率の誘電体よりなる中間材4を用意し、
各基板の方向性指示マーク2を合わせ、この中間
材4を第4図に示すように第1のコンデンサ基板
1と第2のコンデンサ基板3の間にはさむ。場合
によつてはこの中間材4を使用しないで、第1お
よび第2のコンデンサ基板1および3を直接重ね
てもよい。このようにして得られた積層体を焼成
炉に入り、誘電体の所要の温度および時間で処理
し、一体化した複合部品を形成する。 Next, as shown in FIG. 3, an intermediate material 4 made of a dielectric material having an appropriate dielectric constant and having the same shape and dimensions as the first and second capacitor substrates 1 and 3 is prepared.
The direction indicating marks 2 of each substrate are aligned, and the intermediate material 4 is sandwiched between the first capacitor substrate 1 and the second capacitor substrate 3 as shown in FIG. In some cases, the intermediate material 4 may not be used and the first and second capacitor substrates 1 and 3 may be directly stacked. The laminate thus obtained enters a firing furnace and is treated at the required dielectric temperature and time to form an integrated composite part.
このようにして得られた複合部品は、内蔵され
た低容量のコンデンサC1〜C3の電極端部と比較
的高容量のコンデンサC4〜C6の電極端部とが90゜
角度の異なる基板の端面に導出されているから、
低容量コンデンサおよび高容量コンデンサは互い
に相手のコンデンサの引出端子の位置を考慮する
必要なく独立に引出端子の位置を設計できるか
ら、作業性が一段と向上する。また、低容量コン
デンサと高容量コンデンサとを別々に製造するも
のであるから製造効率が良い等の利点もある。 The composite component thus obtained has a 90° angle difference between the electrode ends of the built-in low-capacity capacitors C 1 to C 3 and the electrode ends of the relatively high-capacity capacitors C 4 to C 6 . Because it is led out to the edge of the board,
Work efficiency is further improved because the positions of the output terminals of the low-capacity capacitor and the high-capacity capacitor can be designed independently without having to consider the positions of the output terminals of the other capacitor. Furthermore, since the low capacitance capacitor and the high capacitance capacitor are manufactured separately, there are also advantages such as good manufacturing efficiency.
上記複合部品の基板を例えば混成集積回路の基
板として利用する場合には、第5図に示すように
焼成後の基板5の表面にガラス被覆6を施こし、
各コンデンサC1〜C6の電極端部から基板平面部
にかけて例えばAg−Pdペーストのような導電ペ
イントを被着して引出端子7を形成する。なお、
混成集積回路の基板として利用しない場合でも、
少なくとも引出端子7は形成する必要がある。図
示の例では電極端部が露出していない部分にも引
出端子が形成されているが、これは作業を簡単に
するためであり、不必要な部分にはなくてもよ
い。ガラス被覆6はなくてもよいが、回路パター
ンを形成するとこの回路パターンと内部電極の間
に寄生容量が生じるので、この寄生容量を減少さ
せるためガラス被覆6はある方が好ましい。 When the substrate of the above composite component is used as a substrate of a hybrid integrated circuit, for example, as shown in FIG. 5, a glass coating 6 is applied to the surface of the substrate 5 after firing,
A conductive paint such as Ag-Pd paste is applied from the electrode end of each capacitor C 1 to C 6 to the flat surface of the substrate to form a lead terminal 7 . In addition,
Even if it is not used as a substrate for a hybrid integrated circuit,
At least the lead terminal 7 needs to be formed. In the illustrated example, lead terminals are also formed in areas where the electrode ends are not exposed, but this is done to simplify the work and may not be provided in unnecessary areas. Although the glass coating 6 may not be provided, since a parasitic capacitance is generated between the circuit pattern and the internal electrodes when a circuit pattern is formed, it is preferable to include the glass coating 6 in order to reduce this parasitic capacitance.
次に、第6図に示すように、ガラス被覆6上に
所定の回路パターン8を形成し、さらに第7図に
示すように所定の電子部品、例えば抵抗Rおよび
トランジスタTを塔載する。かくして、複合部品
の基板5に抵抗RおよびトランジスタTを塔載し
た混成集積回路が形成される。 Next, as shown in FIG. 6, a predetermined circuit pattern 8 is formed on the glass covering 6, and further, as shown in FIG. 7, predetermined electronic components such as a resistor R and a transistor T are mounted. In this way, a hybrid integrated circuit is formed in which the resistor R and the transistor T are mounted on the composite component substrate 5.
このように構成すると、複雑な回路構成であつ
ても、所定位置に内蔵コンデンサの電極引出端子
を形成することによつてプリント回路パターンに
絶縁交差させるべき個所が非常に少なくあり、従
つて最小限のジヤンパーの使用で足りることにな
り、回路設計が容易で、小型化できる等の利点が
ある。 With this configuration, even if the circuit configuration is complex, by forming the electrode lead terminal of the built-in capacitor at a predetermined position, there are very few places that need to be insulated and crossed over the printed circuit pattern. It is sufficient to use a jumper, which has advantages such as easy circuit design and miniaturization.
なお、ガラス被覆6を施こす場合に、方向性指
示マーク2が隠れないようにすることが好まし
い。また、第6図に示す回路パターン8は単に例
示であり、実際の回路の回路パターンを示すもの
ではない。勿論、第7図の抵抗Rおよびトランジ
スタTの塔載位置、接続関係も単に例示にすぎ
ず、実際の回路を示すものではない。塔載する電
子部品の種類、個数は実際の回路によつて異なる
ものであり、抵抗、トランジスタ以外の部品が塔
載されることもある。また、コンデンサ基板の形
状、寸法あるいは内蔵されるコンデンサの個数、
容量等も必要に応じて種々に変更されるものであ
る。 Note that when applying the glass coating 6, it is preferable that the direction indicator mark 2 is not hidden. Further, the circuit pattern 8 shown in FIG. 6 is merely an example and does not represent a circuit pattern of an actual circuit. Of course, the mounting positions and connection relationships of the resistor R and transistor T in FIG. 7 are merely examples, and do not represent an actual circuit. The type and number of electronic components mounted vary depending on the actual circuit, and components other than resistors and transistors may be mounted. In addition, the shape and dimensions of the capacitor board or the number of built-in capacitors,
Capacity etc. can also be changed in various ways as necessary.
第1図は本考案による複合部品の第1のコンデ
ンサ基板を示す平面図、第2図は本考案による複
合部品の第2のコンデンサ基板を示す平面図、第
3図は本考案に使用される中間材の平面図、第4
図は本考案による複合部品の焼成前の状態を示す
側面図、第5図ないし第7図は本考案による複合
部品の基板を使用して混成集積回路を製造する際
の製造工程の一例を示すそれぞれ概略平面図であ
る。
1:第1のコンデンサ基板、2:方向性指示マ
ーク、3:第2のコンデンサ基板、4:中間材、
5:複合部品の基板、6:ガラス被覆、7:引出
端子、8:回路パターン、C1〜C3:低容量コン
デンサ、C4〜C6:高容量コンデンサ。
FIG. 1 is a plan view showing the first capacitor substrate of the composite component according to the present invention, FIG. 2 is a plan view showing the second capacitor substrate of the composite component according to the present invention, and FIG. 3 is a plan view showing the second capacitor substrate of the composite component according to the present invention. Plan view of intermediate material, 4th
The figure is a side view showing the state of the composite component according to the present invention before firing, and Figures 5 to 7 show an example of the manufacturing process when manufacturing a hybrid integrated circuit using the substrate of the composite component according to the present invention. Each is a schematic plan view. 1: first capacitor board, 2: direction indicator mark, 3: second capacitor board, 4: intermediate material,
5: Composite component board, 6: Glass coating, 7: Output terminal, 8: Circuit pattern, C1 to C3 : Low capacity capacitor, C4 to C6 : High capacity capacitor.
Claims (1)
ターンとにより形成された少なくとも1つの低
容量のコンデンサを内蔵する第1のコンデンサ
基板と、高誘電率の誘電体とコンデンサ電極用
導電パターンとにより形成された少なくとも1
つの比較的高容量のコンデンサを内蔵する第2
のコンデンサ基板とを積層し、焼成して一体化
してなる複合部品において、 前記低容量コンデンサの電極引出端子と前記
高容量コンデンサの電極引出端子とを互いに90
度角度の異なる位置に形成したことを特徴とす
る複合部品。 (2) 前記複合部品上にトランジスタあるいは抵抗
を塔載したことを特徴とする実用新案登録請求
の範囲第1項記載の複合部品。 (3) 前記第1および第2のコンデンサ基板の一隅
には方向指示マークが取り付けられていること
を特徴とする実用新案登録請求の範囲第1項記
載の複合部品。[Claims for Utility Model Registration] (1) A first capacitor substrate containing at least one low-capacitance capacitor formed by a low-permittivity dielectric and a conductive pattern for capacitor electrodes, and a high-permittivity dielectric at least one conductive pattern formed by the body and the conductive pattern for the capacitor electrode.
A second capacitor containing two relatively high capacitance capacitors
In a composite component formed by laminating and baking a capacitor substrate, the electrode lead terminals of the low capacitance capacitor and the electrode lead terminals of the high capacitor capacitor are separated by 90° from each other.
A composite part characterized by being formed at different angles. (2) The composite component according to claim 1, which is a utility model registration, characterized in that a transistor or a resistor is mounted on the composite component. (3) The composite component according to claim 1, wherein a direction indicating mark is attached to one corner of the first and second capacitor substrates.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8475882U JPS58187127U (en) | 1982-06-09 | 1982-06-09 | composite parts |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8475882U JPS58187127U (en) | 1982-06-09 | 1982-06-09 | composite parts |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS58187127U JPS58187127U (en) | 1983-12-12 |
JPH0115150Y2 true JPH0115150Y2 (en) | 1989-05-08 |
Family
ID=30093684
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8475882U Granted JPS58187127U (en) | 1982-06-09 | 1982-06-09 | composite parts |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58187127U (en) |
-
1982
- 1982-06-09 JP JP8475882U patent/JPS58187127U/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS58187127U (en) | 1983-12-12 |
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