JPH01147857A - Semiconductor memory and manufacture thereof - Google Patents

Abstract

PURPOSE:To increase a storage capacity per unit plane area by so forming opposite electrodes as to include the upper, lower and side faces of a storage electrode. CONSTITUTION:Since opposite electrodes 132a are so formed as to include the upper, lower and side faces of a storage electrode 130a, a storage capacity per unit plane area can be increased. A step of laminating a second insulating film 125 and a first conductor film 130 in two layers is continued N times. Further, after the N times continued films 125, 130 are selectively removed, only the N times continued film 125 is isotropically etched, thereby forming a storage electrode 130a of a sectional branch structure. Thus, the area of the storage electrode can be stereoscopically increased within the same plane of the forming region of the electrode 130a.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a semiconductor device and its manufacturing method, particularly a highly integrated, high-performance dynamic random access memory (DRAM).
Regarding the structure of the cell and its formation method, the purpose is to increase the area of the storage electrodes of the memory cell by stacking them in the same plane and increase the storage capacity. A dynamic memory cell includes a transfer transistor having a pair of impurity diffusion regions and a gate electrode formed in a gate electrode, and a storage capacitor, the surface of the transfer transistor is covered with an insulating film, and the storage capacitor is ! An integrated integrated electrode whose end portion extends above the gate electrode and field insulating film is connected to one of the impurity diffusion regions through an opening formed in the film and is spaced apart from the insulating film by a predetermined distance. a storage electrode made of a first conductive film; a dielectric film formed to wrap around the storage electrode exposed from the opening; a gap between the insulating film and the storage electrode; an upper surface and side surfaces of the storage electrode; and a counter electrode made of a second conductive film formed on the top of the device, and the second device includes a pair of impurity diffusion regions formed in a region defined by the field insulating film. A dynamic memory cell includes a transfer transistor having a gate electrode and a storage capacitor, the surface of the transfer transistor is covered with an insulating film, and the storage capacitor is configured to diffuse the impurity through an opening formed in the insulating film. an integral first insulating film connected to one of the regions and having an end extending onto the gate electrode and the field insulating film with a predetermined gap from the insulating film; and the first conductive film. a storage electrode having a second conductive film formed in a gap between the body film and the insulating film and connected to a portion extending upward of the first conductive film; and exposed from the opening. A dielectric film formed to wrap around a second conductor film, a gap between the first conductor film and the second conductor film, and a top surface and side surface of the first conductor film. and a counter electrode formed of a third conductive film, and the third device includes a pair of impurity diffusion regions formed in a region defined by the field insulating film and a gate electrode. and a dynamic memory cell having a storage capacitor, a surface of the transfer transistor is covered with an insulating film, and the storage capacitor is connected to the impurity diffusion region through an opening formed in the insulating film. an integral first electrode connected to one side and whose end portion in the insulating film extends onto the gate electrode and the field insulating film;
a second conductive film formed overlapping the first conductive film with a predetermined gap and connected to the first conductive film over the opening; a dielectric film formed to wrap around the storage electrode exposed from the opening, and a third conductive film formed to face the entire surface of the storage electrode exposed from the opening. A first manufacturing method thereof includes a step of forming a transfer transistor including a pair of impurity diffusion regions and a gate electrode in a region on a semiconductor substrate defined by a field insulating film. , a step of forming an insulating first film covering the transfer transistor, a step of laminating a second film made of a material different from the first insulating film, and a step of forming one of the impurity diffusion regions. forming an exposed opening; stacking a first conductive film within the opening and on the second film and patterning it to form a storage electrode; and forming a second film by isotropic etching. selectively removing the insulating first film and the first conductive film; forming a dielectric film on the entire surface of the first conductive film exposed from the opening; and then removing the insulating first film and the first conductive film. forming a second conductive film on the dielectric film including a gap therebetween to form a counter electrode; forming a transfer transistor including a pair of impurity diffusion regions and a gate electrode in a region; forming an insulating first film covering the transfer transistor; and forming a first insulating film on the first film. a step of forming a conductor film; a step of forming a second film on the first conductor film using a material that is different from the first film; the first film and the first conductor; forming an opening extending through the film and the second film to one of the impurity diffusion regions; and forming an opening on the impurity diffusion region exposed in the opening, on the inner surface of the opening, and on the second film. a step of forming a second conductor film; a step of patterning the first and second conductor films and the second film; and a step of selectively removing the second film by isotropic etching. a step of forming a dielectric film so as to wrap around the exposed surface of the 1.2 conductor film; and a step of depositing a third conductor film so as to wrap around the dielectric film. The third manufacturing method includes forming a transfer transistor including a pair of impurity diffusion regions and a gate electrode in a region on a semiconductor substrate defined by a field insulating film, and forming an insulating transistor covering the transfer transistor. forming a first film in the first film; forming a first opening in the first film to expose one of the impurity diffusion regions; and forming a second film in the first opening and on the first film. forming a first conductor film on the first conductor film; laminating a second film made of a material different from the first film on the first conductor film; forming a second opening that exposes the first conductive film by removing the second film; and forming a second conductive film within the second opening and on the second film. a step of patterning the first and second conductor films and a second film; a step of selectively removing the remaining second film by isotropic etching; and a step of selectively removing the remaining second film by isotropic etching. .A step of forming a dielectric film so as to wrap around the second conductor film, and a step of forming a third conductor film so as to wrap around the dielectric film.

[Industrial application field]

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a TII structure of a highly integrated, high-performance dynamic random access memory (DRAM) cell and a method for forming the same.

[Conventional technology]

FIG. 9 is an explanatory diagram of a conventional DRAM cell.

FIG. 2(a) is an electrical circuit diagram of a DRAM cell.

In the figure, T is a MOS that transfers data (charge)
Transfer transistor, C1, composed of transistors, etc.
is a storage capacitor that stores charges, WL is a word line, and BL is a bit line. Note that 6 is a storage electrode, 7 is a dielectric film, and 8 is a storage electrode.
is the counter electrode.

FIG. 2B is a cross-sectional view showing the DRAM cell structure. In the figure, 1 is a Si substrate such as a p-type epitaxial layer, 2 is
3.4 is a field oxide film (SiO□ film) formed by the LOGOS method, etc., and 3.4 is an impurity diffusion layer formed by diffusing A, ° ions, etc., and is used as the source or drain of the transfer transistor. be. 5 is word line WL
CVD oxide film (Si0g film)
etc. Reference numeral 6 denotes an electrode formed by doping a poly-Si film with impurity ions, and is a storage electrode constituting the storage capacitor C1. 7 is a dielectric film formed of an insulating film such as a 5iot film or a 5iaNn film. Reference numeral 8 denotes an electrode formed by doping impurity ions into a poly-Si film, and is a counter electrode constituting the storage capacitor CI. 9 is opposite 'rH,
I? This is an insulating film that insulates i8, and is a PSG film or the like.

Note that WL is a gate electrode of a transfer transistor formed of a poly-Si film or the like, and is a word line. Further, BL is a bit line formed of a poly-Si film or a polycide film doped with impurities.

[Problem that the invention seeks to solve]

According to the prior art, as the degree of integration of semiconductor devices increases and the size of semiconductor elements becomes smaller, the area of a DRAM memory cell becomes smaller and smaller.

For this reason, the storage capacitance C1 of the memory cell, which depends on the area of the storage electrode, is forced to decrease with integration and miniaturization.

Therefore, as the storage capacitance CI decreases, there are problems in that soft errors due to the incidence of α rays increase and the reliability of the memory characteristics of the DRAM decreases.

The present invention has been created in view of the problems of the conventional example, and provides a semiconductor device and its manufacture that can three-dimensionally increase the storage electrode area of a memory cell within the same plane to increase the storage capacity. The purpose is to provide a method.

[Means for solving problems]

As an embodiment of the semiconductor device and its manufacturing method of the present invention is shown in FIGS. Si region 12
3,124 and a gate electrode WL0, and a dynamic memory cell comprising a storage capacitor C0, the surface of the transfer transistor T0 is covered with an insulating film 125, and the storage capacitor C0 is [125] connected to one of the impurity diffusion regions 123, 124 through an opening formed in the insulating film 1;
25, with a predetermined distance between the ends of the gate electrodes i! ii W L 6 and field insulation 11!212
2, a dielectric film 131 formed to wrap around the storage electrode 130a exposed from the opening, and a dielectric film 131 formed to surround the storage electrode 130a exposed from the opening; It is characterized by comprising a gap with the storage electrode 130a and a counter electrode 132a made of a second conductive film 132 formed on the top and side surfaces of the storage electrode 130a, and the second device is field insulated It. ! :! 22, a transfer transistor T2 having a pair of impurity diffusion regions 23, 24, a gate Mj, poles WL3, WL, and a storage capacitor C2; Transfer transistor 7.
The surface is covered with an insulating film 25, and the storage capacitor C is connected to one of the impurity diffusion regions 23 and 24 through an opening formed in the insulating film 25, and is connected at a predetermined distance to the insulating film 25. With a gap, the end portion is connected to the gate electrode WL3.
, WL, and an integral first conductive film 27 extending onto the field insulating film 22; a first conductive film formed in a gap between the first conductive film 27 and the insulating film 25; A storage electrode 3 having a second conductor film 30 connected to a portion extending upwardly of the body membrane 27
0a, a dielectric film 31 formed to wrap around the second conductor film 30 exposed from the opening, and the first conductor film 2.
7 and the second conductor film 30, and a counter electrode 32a made of a third conductor film 32 formed on the top and side surfaces of the first conductor film 27. The third device is a pair of impurity diffusion regions 43 formed within a region defined by a field insulating film 42.
．． 44, a transfer transistor T having gate electrodes WL3 and WL6, and a dynamic memory cell comprising a storage capacitor C1, the lower two surfaces of the transfer transistor are covered with an insulating film 45, and the M laminated layer 1c is: The insulation II! It is connected to one of the impurity diffusion regions 43 and 44 through the opening formed in J45, and is connected to the insulating film 4.
5, the end portion is the gate electrode WL.

, WL&, and an integrated first conductive film 48 extending onto the field insulating film 42, overlapping the first conductive film 48 and leaving a predetermined gap therebetween;
a storage electrode 51a having a second conductive film 51 connected to the first conductive cavity 48 above the opening; and a dielectric film 52 formed to wrap around the storage electrode 51a exposed from the opening. and a counter electrode 53a made of a third conductor IF253 formed to face the entire surface of the storage electrode 51a exposed from the opening.
A pair of impurity diffusion regions 123 and 124 and a gate electrode W L are provided in a region on the semiconductor substrate 121 defined by 22 .

forming a first insulating film 125 covering the transfer transistor T0; and then forming a second insulating film 125 of a material different from the first insulating film 125.
a step of stacking the film 126 of the impurity diffusion region 12;
forming an opening 129 that exposes one of the second II' 2126 and the inside of the opening 129;
First conductor E! on top! 130 is laminated and patterned to form the storage electrode 130a, and isotropic etching is performed to form the second IPE! 126 selectively removing the first conductor film 13 exposed from the opening 129;
a step of forming a dielectric film 131 on the entire surface of the insulating film 131;
The second manufacturing method is characterized in that it includes a step of forming a second conductor IPJ 132 on the dielectric film 131 including the gap with the field insulating film 25 to form a counter electrode 132a. A pair of impurity diffusion regions 23 and 24 and a gate electrode wt3 are provided in the defined region on the semiconductor substrate 21,
, W.L.

A step of forming a transfer transistor T2 including the step of forming the transfer transistor T! a step of forming an insulating first film 25 covering the first film 25; a step of forming a first conductor v, 27 on the first film 25; a step of forming the first conductor v, 27 on the first conductor film 27; a step of forming a second 1F22B with a material different from that of the first Wa25;
II! 25, the first conductor film 27 and the second film 2
forming an opening 29 penetrating through the impurity diffusion region 23 and reaching one of the impurity diffusion regions 23 and 24; a step of forming a second conductor film 30 thereon; a step of patterning the first and second conductor films 27, 30 and the second film 28; and a step of patterning the second conductor film 30 by isotropic etching. a step of forming a dielectric film 31 so as to wrap around the exposed surface of the first and second conductive films 27 and 30; The third manufacturing method includes the step of depositing a conductive film 32 on a semiconductor substrate 4 defined by a field insulating film 42.
A pair of impurity diffusion fiI regions 43 and 44 and gate electrodes WL3 and WL are provided in the region above 1.

forming a first insulating film 45 covering the transfer transistor T3; forming a first opening 47 in the first film 45; a step of exposing one of the impurity diffusion regions 43 and 44; a step of forming a first conductor film 48 in the first opening 47 and on the first W 145; membrane 48
a step of laminating a second film 49 made of a material different from the first film 45 thereon, and a step of laminating the second film 49 on the first opening 47;
9 to form a second opening 50 exposing the first conductor 115148; forming a second conductor film within the second opening 50 and on the second film 49; 51, patterning the first and second conductor films 48, 51 and the second film 49, and selectively removing the remaining second film 46 by isotropic etching. a step of forming a dielectric film 52 to wrap around the first and second conductor films 48.51; and a step of forming a third conductor film 53 to wrap around the dielectric W152. The above object is achieved.

[For production]

According to the semiconductor memory device of the present invention, since the opposing electrode is formed to include the upper surface, lower surface, and side surface of the storage electrode, the storage capacity per unit plane area can be increased compared to the conventional example. .

Further, according to the manufacturing method of the present invention, the second insulation layer,
continuing the step of laminating the first conductive film in two layers N times; selectively removing the insulating film and the conductive film that have been successively repeated N times; By isotropically etching only the continuous insulating film, it is possible to form a storage electrode having a dendritic cross-sectional structure.

Therefore, the storage electrode area can be three-dimensionally increased within the same plane of the storage electrode formation region.

This makes it possible to increase storage capacity.

[Example] Next, an example of the present invention will be described with reference to the drawings.

The first to eighth illustrations are explanatory diagrams of a semiconductor device and its manufacturing method according to an embodiment of the present invention, and FIG. 1 is a sectional view of a DRAM cell according to a first embodiment of the present invention.

FIG. 5A is a structural diagram of a DRAM cell according to the first embodiment. In the figure, 121 is a Si substrate having a p-type epitaxial layer, 122 is a field oxide film selectively oxidized, and 123 and 124 are This is an impurity diffusion layer formed by diffusing impurities such as As'' ions, and is the source and drain of the transfer transistor T0.

WL is a gate electrode formed of a poly-Si film or the like, and an extension of this gate electrode becomes a word line in a DRAM cell. Further, a bit line (not shown) is connected to the source 124.

125 is an insulating film etc. that insulates the gate electrode WL,
5iJa II! formed by. These constitute a transfer transistor T.

Further, 130a is a storage electrode formed of a conductive film, for example, a poly-Si film containing impurities, and has a dendritic structure in cross section. A dielectric film 131 is formed by thermally oxidizing the surface of a poly-Si film 130a containing impurities. Note that 132 is a conductive film, for example, a counter electrode formed of a poly-Si film containing impurities;
Storage capacitance C0 together with storage electrode 130a and dielectric film 131
form.

These constitute the DRAM cell according to the first embodiment.

Figure (b) shows another DRAM according to the first embodiment of the present invention.
This is a cell structure diagram, and in the diagram, accumulation? ili 13
PolySi film 1 containing impurity ions forming 0a
30 is provided in the upper part in a plurality of tree branches. This increases the surface area of the dielectric film 131 surrounding the storage electrode 130a, making it possible to increase the storage capacitance C(1') compared to the DRAM cell shown in FIG.

FIG. 2 is a sectional view of a DRAM cell according to a second embodiment of the invention.

FIG. 2(a) is a structural diagram of a DRAM cell according to the second embodiment. In the figure, 21 is a Si substrate having a P-type epitaxial layer, 22 is a field oxide film subjected to selective LOCOS oxidation, and 23 and 24 are This is an impurity diffusion layer formed by diffusing impurities such as As'' ions, and is an impurity diffusion layer formed by diffusing impurities such as As'' ions.
2 sources and drains.

WL3 and WL4 are gate electrodes formed of a poly-Si film or the like, and these gate electrodes WL3 and WL.

The extended line becomes the word line in the DRAM cell. Further, a bit line (not shown) is connected to the source 24. Reference numeral 25 denotes an oxide film or the like that insulates the gate voltages tmWL3 and WL4, and is formed of a 5isNa film. These constitute a transfer transistor T.

Further, 30a is a conductive film, for example, polysilicon containing impurities.
It is a storage electrode formed of an i-film and has a cross-sectional dendritic structure. A dielectric film 31 is formed by thermally oxidizing the surface of the poly-Si film 30a containing impurities. Note that 32 is a counter electrode formed of a conductive film, for example, a poly-Si film containing impurities, and forms a storage capacitor Ct together with the storage electrode 30a and the dielectric film 31.

These constitute a DRAM cell according to the second embodiment.

Figure (b) shows another DRAM according to the second embodiment of the present invention.
This is a structural diagram of a cell, and in the figure, the storage charge +m30a connects the gate electrodes WL3, WL, of the transfer transistor T2' to M
! , the edge 5t3N is provided directly on the membrane 25. As a result, the surface area of the dielectric film 31 surrounding the storage electrode 30a is reduced, compared to the DRAM cell shown in FIG.
Although the storage capacitance cz' is reduced, it is possible to omit the manufacturing process related to the SiO2 film 26.

FIG. 3 is a sectional view of a DRAM cell according to a third embodiment of the present invention, and FIG.
It is a structural diagram of a cell.

In the figure, similarly to the DRAM cell according to the first embodiment, 41 is an epitaxial layer etc. of Si! +&, 42 is a field oxide film, 43.44 is an impurity expansion km, and is the source and drain of the transfer transistor T. WLs,
WLh is a gate electrode and a word line.

45 is an insulating film or the like, which is a 5tJn film. These constitute a transfer transistor T similarly to the DRAM cell of the first embodiment.

Further, 51a is a storage electrode formed of a poly-Si film containing impurities, and has a cross-sectional dendritic structure. Note that 52 is a dielectric film, and 53 is a counter electrode. Further, C1 is a storage electrode 51a.

This is a storage capacitor composed of a dielectric film 52 and a counter electrode.

These constitute the DRAM cell according to the third embodiment, and since the storage electrode area is slightly smaller than that of the second DRAM cell, the storage capacity is slightly smaller.
The poly-Si films constituting the storage electrodes have a large contact area with each other, making it difficult for troubles such as peeling to occur.

FIG. 4 is a process diagram for forming a DRAM cell according to the first embodiment of the present invention.

In the figure, first, Si-based 4Fi, such as an epitaxial layer, is
121 is thermally oxidized by selective locos ([,0CO3) method or the like to form field oxidation 'v122, and desired impurity ions such as A and 1 ions are implanted into the Si substrate 121. After that, heat treatment is performed, and n.

Impurity diffusion ff1123 and 124 are formed. Note that n゛ impurity diffusion 11123 and 124 are transfer transistors T0.
becomes the source and drain of

Furthermore, a gate electrode W Lo is formed using a poly-Si film or the like via a 5tyx film (gate oxide film). Furthermore, gate TLl? i8W Lo becomes a word line in the DRAM cell ((a) in the same figure).

Next, the gate electrode WL is formed using a 0Si3N4 (or Stow) film 125 with a thickness of about 1000 by low pressure CVD.
and Sing (
or 5iJJ) film 126 is formed (FIG. 5(b)).

Next, using a resist film (not shown) as a mask, the Stag film 12 is
6, Si3N, and the film 125 are opened by anisotropic etching such as RIE to form an opening 129.

Note that the opening 129 becomes a contact hole between the storage electrode 130a and the drain 124 in a later process ((C) in the same figure).
.

Next, on the entire surface of the Si substrate 121 provided with the opening 129, poly 5j17130 doped with OS pure ions is formed to a thickness of about 1000 by low-pressure CVD or the like, and patterned (FIG. 4(d)).

Next, the Sing film 126 is completely removed by isotropic etching using an aqueous solution of HF (hydrofluoric acid), and the storage electrode 13 is removed.
Form 0a. Note that the gate electrode WL.

The 5isNa M 125 that insulates the storage electrode 130a is not etched even when immersed in an HF solution, and as a result, the storage electrode 130a has a dendritic structure in cross section (FIG. 2(e)).

Next, the surface of the storage electrode 130a is thermally oxidized to form a dielectric film 131 such as a SiO□ film (FIG. 1(f)).

Further, a poly S+il 32 doped with impurity ions surrounding the dielectric film 131 is formed on the entire surface by low pressure CVD method or the like, and by patterning it, the counter electrode 13
2a (FIG. 2(g)).

As a result, a DRAM cell according to the first embodiment as shown in FIG. 1(a) can be manufactured.

Note that PSG is used as an insulating film covering the counter electrode 132a.
Insulation processes for films, etc., wiring processes for bit lines, etc. will continue.

FIG. 5 is a process diagram for forming a DRAM cell according to a second embodiment of the present invention.

In the figure, first, a Si substrate 21 such as an epitaxial layer is thermally oxidized by selective LOCO3 method or the like to form a field oxide film 22, and then desired impurity ions such as S1 ions are implanted into the Si substrate 21. . Thereafter, heat treatment is performed to form n' impurity diffusion layers 23 and 24. Note that the impurity diffusion layers 23 and 24 are the transfer transistor T2.
becomes the source and drain of

Furthermore, poly-Si is formed through SiO□119 (gate oxide film).
Gate electrodes WL3, WL are formed using a film or the like.

Note that the gate electrodes WL3, WL become word lines in the DRAM cell. Next is the gate electrode WL.

, WL, are insulated by a 0iO□ (or 5i3N4) film 25 with a thickness of about 1,000 layers formed by low-pressure CVD (
Figure (a)).

Next, on the entire surface of the 5tJa film 25, a film with a thickness of 1,000 yen is applied to the S impurity
A poly-Si film 27 doped with approximately 0 impurity ions,
It is formed by sequentially laminating layers of about 1,000 nitride oxide films using a low pressure CVD method or the like. In addition, the SiO! 111i
The step of laminating the poly-Si film 26 and the poly-Si film 27 into two layers is performed N times continuously as desired.

Furthermore, the resist film 33 is patterned (FIG. (b)).
).

Next, using the patterned resist film 3 as a mask, the 5iOt film 28, the poly-Si film 27 containing impurity ions, the Sing film 26, and the 5itN4 film are selectively removed by anisotropic etching such as RIE to form an opening. Then, an opening 29 is formed. The etching gas used was CF, 102 for the SiO□ film, and C(1,1) for the poly-Si film.
Use 0□.

Further, the entire surface of the 5i02 film 28 with the opening 29
A poly-5i film 30 containing about 71,000 impurities is formed by method D (FIG. 3(C)).

After that, using a resist film (not shown) as a mask, the poly-Si film 30, the SiO□ film 28, and the poly-Si film 27 are subjected to RIE.
Patterning is done by anisotropic etching such as (see the same figure).
d)).

Next, by isotropic etching with HF (hydrofluoric acid) etc., the Si
The O□ film 28 and the SiO□ film 26 are completely removed to form a storage electrode 30a. Note that the gate electrodes W L s, WL
The 5iJ4 film 25 that insulates the substrate a is not etched even if it is exposed to the HF solution. As a result, the storage electrode 30a has a dendritic cross-sectional structure. Note that the insulating film 25 is a SiO□ film, and the other insulating film 11
The same result can be obtained by using phosphoric acid etching in the formation step of the same figure (e) using g26.28 as a 5iJ4 film (the same figure (e)).

Next, the surface of the storage electrode 30a is thermally oxidized to form SiO□
A dielectric film 31 such as a film is formed (FIG. 3(f)).

The subsequent formation process is similar to the DRAM cell according to the first embodiment, in which the impurity ions surrounding the dielectric material [1] and the doped poly-Si film 32 are patterned to form a counter electrode 32a. As a result, a DRAM cell according to the second embodiment as shown in FIG. 2(a) can be manufactured.

FIG. 6 is a process diagram for forming another DRAM cell according to the second embodiment.

In the figure, first, a Si substrate 21 such as an epitaxial layer is thermally oxidized by selective LOCO3 method or the like to form a field oxidation 622, and then desired impurity ions such as As' ions are implanted into the ST5 plate 21. Thereafter, heat treatment is performed to form n' impurity diffusions N23 and N24. Note that the n impurity diffusion layers 23 and 24 are transfer transistors T2.
becomes the source and drain of

Furthermore, 5totv, poly-Si via (gate oxide film)
Gate electrodes wt, z, WL4 are formed using a film or the like.

Note that the gate electrodes W L s and W L a are DRAM
This becomes the word line in the cell. Next, gate ring 5W
L s, WLa formed by low pressure CVD method, film thickness 1000
It is insulated by a film 25 of approximately 0<i01 (or 5iJ4) (FIG. 4(a)).

Next, StJ is coated on the entire surface of the film 25 with a film r7. A poly 5ill film 27 doped with about 1,000 impurities and a 5-impurity T film with about 1,000 film ffs are sequentially formed by a low pressure CVD method or the like. In addition, the 5iOzF! The step of laminating the poly-Si film 26 and the poly-Si film 27 into two layers is performed using N@mbl as desired.

After that, the resist film 33 is patterned (FIG. (b)).
).

Next, using the patterned resist film 33 as a mask, the poly-Si film 27 containing SiO□11928 and impurity ions and the 5iJn film are selectively removed by anisotropic etching such as RIE to form an opening 29. Form. The etching gas was 5tozrI.

CF4102 for poly-Si film, CCl41 for poly-Si film
0□ is used ((C) in the same figure).

Further, on the entire surface of the 5tOzl 122 B provided with the opening 29, a poly 5tpao containing impurities with a film thickness of about 1000λ is formed by the CVD method, and then, using a resist film (not shown) as a mask, the polySi film 30 and the SiO2 film 28 are formed. and the poly-Si film 27 are patterned by anisotropic etching such as RIE (FIG. 4(d)).

Next, by isotropic etching with HF (hydrofluoric acid) etc., the Si
The O□ film 28 is entirely removed to form a storage electrode 30a.

Note that 5i3Na insulating the gate electrodes WL, , WL,
The film 25 is not etched even if exposed to the HF solution. As a result, the storage electrode 30a has a dendritic cross-sectional structure ((e) in the same figure).
).

After the formation step shown in FIG. 3(e), the surface of the storage electrode 30a is thermally oxidized to form a dielectric film 31 such as a SiO□ film, as in the first embodiment, and then an impurity film is formed as the counter electrode 32. This is done by forming a poly-Si film doped with ions over the entire surface by CVD.

As a result, another DRAM cell according to the second embodiment as shown in FIG. 2(b) can be manufactured.

FIG. 7 is a process diagram for forming a [) RAM cell according to a third embodiment of the present invention.

In the figure, first, a Si substrate 41 such as an epitaxial layer is thermally oxidized by selective LOCO3 method or the like to form a field oxide film 42, and then desired impurity ions such as As'' ions are implanted into the Si substrate 21. Thereafter, heat treatment is performed to form n° impurity diffusion layers 43 and 44. Note that the n° impurity diffusion layers 43 and 44 become the source and drain of the transfer transistor T.

Furthermore, poly-Si is
Gate electrodes WL3, WL are formed using a film or the like. Note that the gate electrodes WL3 and WL serve as word lines. Then,
The gate electrode WL3, WL is made of 0Si with a film thickness of about 1000.
It is insulated by an sNa film 45 (FIG. 4(a)).

Next, on the entire surface of the 5iJ4 film 45, a 0SiO□ film 46 with a thickness of about 1,000 layers is formed by CVD or the like (see Figure (b).
)).

Next, using a resist film (not shown) as a mask, the SiO□ film 46 and the 6tJ4 film 45 are selectively removed by anisotropic etching such as RIE to form an opening 47. The etching gas is CF.

/01 is used ((C)).

Furthermore, the entire surface of the Si substrate 41 in which the opening 47 is provided is coated with a polyurethane containing OS pure to a thickness of about 1,000. A Si film 48 is formed by a CVD method, and a StO□ film 49 is further formed on the entire surface of the poly-Si film 48 by a CVD method or the like.

((d) in the same figure).

Next, Si is etched by RIE using CF410□ gas.
An opening 50 is formed between the O□ films 49 and exposing the 3% poly film 48 (FIG. 4(e)).

Thereafter, a poly-Si film 51 containing impurity ions is formed on the entire surface of the SiO□ film 49 provided with the opening 50 by low pressure CVD or the like (FIG. 4(f)).

Next, using a resist film (not shown) as a mask, the poly-Si film 5
1. Patterning the Si film 48 between the SiO□ films 49 by RIE using a predetermined gas (FIG. (g))
. After that, the remaining Sio□ film 49 and the six sides of the SiO□ film 46 were removed by isotropic etching using HF solution, etc.
Accumulation T! J, form the pole 51a. Note that the gate electrode W
The 5isNa film 45 that insulates L3 and WL is not etched even if it is immersed in HF solution. Further, the storage electrode 51a has a dendritic cross-sectional structure ((g) in the same figure).

Note that the process after the formation step shown in FIG. 3(h) is the same as that of the first embodiment, and by forming the dielectric film 52 and the counter electrode 53, the third embodiment as shown in FIG. 3(a) is formed. DR related to
AM cells can be manufactured.

In addition, in the 2.3 embodiment, the first board') S
i film (27, 48) and a second poly-Si film (30, 5
1) was patterned using the same resist, but after patterning the first poly-Si film (27, 48), the third poly-Si film (27, 48) was patterned.
Alternatively, a SiO□ film (28, 49) may be formed. In this case, after etching the second poly-Si film (30, 5'l), the third SiO□ film (27, 48'l) is etched using the same resist.
) there is no need to etch.

In addition, in Example 2.3, a second 540g film (
By omitting the formation of 26, 46), Fig. 2(b)
, as shown in FIG. 3(b). Another DRAM cell according to the third embodiment can be manufactured.

FIG. 8 shows each DRA according to the 1.2.3 embodiment of the present invention.
FIG. In the figure, WL3, W shown by solid lines
L3 or WL, , WL, or WL.

is a word line, and BL indicated by a dashed line is a bit line.

In addition, 130a, 30a, or 51a shown by a two-dot chain line is the stored electricity 1j. Further, 54 is a source contact portion connecting the source 23 or 43 of the transfer transistor T2 and the bit line, and 29 or 47 is the M product electrode 130a, 30
a or 51a and the drain 124 of the transfer transistor T2
．． 24 or 44.

In this way, according to the DRAM cell No. 1.2.3, since the storage electrode 130a, 30a or 51a has a dendritic cross-sectional structure, the area of the storage electrode sandwiching the dielectric film 131°31 or 52 can be reduced from that of the conventional example. can be increased compared to This makes it possible to increase the storage capacitances Co, Cz, and Cz.

Further, according to the method for manufacturing a DRAM cell in No. 1.2.3,
SiO□ film 126, 26.28 or 46.49 and poly5itP227.130.30 containing impurity ions
or 48.51 in two layers N times, and 5iO2ll1126.26.2 continued N times.
8 or 46.49 and the poly 5i film 27.130.30 or 48.51, followed by N
Sin, membrane 126.26.2B or 46.4 times continued
By isotropically etching only 9, it becomes possible to form storage electrodes 130a, 30a, or 51a having a dendritic cross-sectional structure.

For this purpose, an M-product electrode 130a as shown in FIG.

The storage electrode area can be three-dimensionally increased within the same plane of the formation region of 30a or 51a. This makes it possible to increase the storage capacitances co, ct, and c3.

〔Effect of the invention〕

As explained above, according to the present invention, the storage electrode area can be increased three-dimensionally. Therefore, according to the present invention, it is possible to form about 2 to 3 times as many n layers as the storage capacitor formed in the same plane in the conventional example.

Further, according to the present invention, since the storage capacity can be increased, it is possible to significantly reduce soft errors caused by the incidence of alpha rays, and to improve the reliability of the memory characteristics of the DRAM.

[Brief explanation of the drawing]

FIG. 1 shows the DI? according to the first embodiment of the present invention. FIG. 2 is a structural diagram of a DRAM cell according to a second embodiment of the present invention, and FIG. 3 is a structural diagram of a DRAM cell according to a third embodiment of the present invention.
R drawing, FIG. 4 is a process diagram for forming a DRAM cell according to the first embodiment of the present invention, FIG. 5 is a process diagram for forming a DRAM cell according to a second embodiment of the present invention, and FIG. FIG. 7 is a diagram of the formation process of another DRAM cell according to the second embodiment of the present invention; FIG. 7 is a diagram of the formation process of another DRAM cell according to the third embodiment of the invention; FIG. FIG. 9 is a plan view of a DRAM cell according to an embodiment. FIG. 9 is an explanatory diagram of a DRAM cell according to a conventional example. (Explanation of symbols) T3, T, ~T, ... transfer transistor, C,, C,
~C1... Storage capacity, 1.121, 21.41... Si substrate (semiconductor substrate)
, 2.122, 22.42... Field oxide film (field insulating film), 3.123, 23.43... Drain (impurity diffusion N
), 4.124, 24.44... Source (impurity expansion n
t layer), 5, 125.25.45...Si3N4 film (insulation #), 6.130a, 30a, 51a -N-T
t-pole, 7, 131, 31.52... dielectric film, 8
, 132. , 32. , 53. ...Counter electrode, 9...
PSG film, 126.26.28, 46.49...SiO□ film (insulating film), 27, 130, 30, 32.48, 51.53
... Poly Si film (conductor film), 29.47... Opening (drain contact part), 50... Opening, 54... Source contact part, tag. , tag, enemy 1 ~ sushi, ... word line (gate electrode), BL, BL, ... bit line. C0 storage capacity First straightening diagram of DR H1 cell according to the first embodiment of the present invention
Fig. 2 Groove diagram of DR, φ1 cell according to the third embodiment 1i of the present invention Fig. 3 (a) (b) (c) Forming process of the DRAM cell according to the first embodiment of the present invention Figure 4 (Part 1) (e) (f) Process of forming the DRAM cell according to the first embodiment of the present invention Figure 4 (Part 2) Figure 4 (Part 2) Formation process of the DRAM cell according to the first embodiment of the present invention Figure 4 (Part 3) (C) Forming process diagram of a DRAM cell according to the second embodiment of the present invention Figure 5 (Part 1) (d) (e) Second embodiment of the present invention Figure 5 (Part 2) (f) Forming process of a DRAM cell according to the second embodiment of the present invention Figure 5 (Part 3) (c) Figure 5 (Part 3) (c) Formation process diagram of another DRA 1% 1 cell according to the embodiment 6 Figure (Part 1) (d) (e) Another DRA and Vl seven paste formation process diagram according to the second embodiment of the present invention No. 6 Figure (Part 2) During the formation process of another DRAM cell according to the second embodiment of the present invention Figure 6 (Part 3) (a) (b) (c) DRAM according to the third embodiment of the present invention Figure 7 (Part 1) (f) During the cell formation process Figure 7 (Part 2) (h) Figure 7 (Part 2) (h) During the formation process of the DRAM cell according to the third embodiment of the present invention Figure 7 (Part 3) during the formation process of such a DRAM cell

Claims (23)

[Claims] (1) A pair of impurity diffusion regions (123, 1
A dynamic memory cell includes a transfer transistor (T_0) having a gate electrode (WL_0) and a storage capacitor (C_0);
T_0) surface is covered with an insulating film (125), the storage capacitor (C_0) is connected to one of the impurity diffusion regions (123, 124) through an opening formed in the insulating film (125), and The ends of the gate electrode (WL_0) and the field insulating film (125) are arranged at a predetermined distance from the insulating film (125).
22) a storage electrode (130a) made of an integral first conductive film (130) extending above; and a dielectric film (131) formed to wrap around the storage electrode (130a) exposed from the opening. ), and the insulating film (
125) and the storage electrode (130a), and a counter electrode (132a) formed of a second conductive film (132) formed on the upper surface and side surfaces of the storage electrode (130a). Characteristic semiconductor memory device. (2) The first conductor film (130) and the insulating film (1
25), each having a plurality of conductive films formed with a gap therebetween and connected to a portion extending upwardly of the first conductive film (130). The semiconductor memory device according to scope 1. (3) A pair of impurity diffusion regions (23, 24) formed within the region defined by the field insulating film (22)
A dynamic memory cell includes a transfer transistor (T_2) having a gate electrode (WL_3, WL_4) and a storage capacitor (C_2), the surface of the transfer transistor (T_2) is covered with an insulating film (25), The storage capacitor (C_2) is connected to one of the impurity diffusion regions (23, 24) through an opening formed in the insulating film (25), and is separated from the insulating film (25) by a predetermined gap. , the end portions are connected to the gate electrodes (WL_3, WL_4) and the field insulating film (
22) an integral first conductive film (27) extending upward; and a first conductive film formed in a gap between the first conductive film (27) and the insulating film (25); a storage electrode (30a) having a second conductive film (30) connected to a portion extending upwardly of the body membrane (27); and a second conductive film (30) exposed from the opening. A gap between the dielectric film (31) formed to enclose the first conductor film (27) and the second conductor film (30), and a gap between the first conductor film (27) and the second conductor film (30). A counter electrode (32) made of a third conductor film (32) formed on the top and side surfaces.
A semiconductor memory device comprising: a). (4) The second conductor film (30) is formed with a gap between the first conductor film (27) and the third conductor film (32). 4. The semiconductor memory device according to claim 3, wherein the storage electrode (30a) is formed so as to cover the entire surface of the storage electrode (30a) exposed from the frontage. (5) The semiconductor memory device according to claim 3, wherein a lower surface of the first conductive film (27) is in contact with the insulating film (25). (6) A pair of impurity diffusion regions (43, 44) formed within the region defined by the field insulating film (42)
a dynamic memory cell comprising a transfer transistor (T_3) having a gate electrode (WL_5, WL_6) and a storage capacitor (C_3), the surface of the transfer transistor (T_3) is covered with an insulating film (45), The storage capacitor (C_3) is connected to one of the impurity diffusion regions (43, 44) through an opening formed in the insulating film (45), and an end of the insulating film (45) is connected to the gate electrode. (WL_5, W
L_6) and a field insulating film (42), an integral first conductive film (48);
48) and a second conductive film (51) formed at a predetermined gap and overlapping with the first conductive film (48), and connected to the first conductive film (48) on the opening. (51a); a dielectric film (52) formed to surround the storage electrode (51a) exposed from the opening; and a dielectric film (52) formed to face the storage electrode (51a) exposed from the opening. Counter electrode (53a) made of third conductor film (53)
A semiconductor memory device comprising: (7) The first conductor film (48) is the insulating film (45).
), and the third
7. The semiconductor memory device according to claim 6, further comprising a conductor film (51) formed thereon. (8) The semiconductor memory device according to claim 6, wherein a lower surface of the first conductive film (48) is in contact with the insulating film (45). (9) A pair of impurity diffusion regions (12
a step of forming a transfer transistor (T_0) including a gate electrode (WL_0) and a gate electrode (WL_0); a step of forming an insulating first film (125) covering the transfer transistor (T_0); A step of laminating a second film (126) made of a material different from that of the first insulating film (125), and an opening (12) exposing one of the impurity diffusion regions (123, 124).
9) and a step of laminating a first conductor film (130) in the opening (129) and on the second film (126) and patterning it to form a storage electrode (130a). selectively removing the second film (126) by isotropic etching; and forming a dielectric film (131) on the entire surface of the first conductive film (130) exposed from the opening (129). and then forming the insulating first film and the first conductive film (1).
A second conductor film (132) is formed on the dielectric film (131) including the gap with the counter electrode (132a).
) A method for manufacturing a semiconductor memory device, the method comprising: (10) the first film (125) is a silicon dioxide film;
The second film (126) is a silicon nitride film, the first film (126) is a silicon nitride film,
10. The method of manufacturing a semiconductor memory device according to claim 9, wherein the second conductive film (130, 132) is a polysilicon film, and the isotropic etching is performed using phosphoric acid. (11) the first film (125) is a silicon nitride film; the second film (126) is a silicon dioxide film;
10. The method of manufacturing a semiconductor memory device according to claim 9, wherein the second conductive film (130, 132) is a polysilicon film, and the isotropic etching is performed using hydrofluoric acid. (12) A pair of impurity diffusion regions (23,
24) and gate electrodes (WL_3, WL_4); and a step of forming an insulating first film (25) covering the transfer transistor (T_2). forming a first conductive film (27) on the first conductive film (25); and forming a second conductive film (27) on the first conductive film (27) using a material different from the first film (25). forming the impurity diffusion region (28) through the first film (25), the first conductor film (27) and the second film (28);
3, 24), and the step of forming an opening (29) leading to one of the openings (29), on the impurity diffusion region (23) exposed in the opening (29), on the inner surface of the opening (29), and on the second film. (28)
a step of forming a second conductor film (30) on the first and second conductor films (27, 30) and the second conductor film (2);
8), selectively removing the second film (28) by isotropic etching, and wrapping the exposed surfaces of the first and second conductor films (27, 30). A step of forming a dielectric film (31) as shown in FIG.
32) A method for manufacturing a semiconductor memory device, comprising the step of depositing a. (13) The first conductor film (27) and the first film (
25), a third film (26) made of a different material from the first film (25) is stacked, and in the isotropic etching step, the third film (26) is laminated together with the second film (28). 13. The method of manufacturing a semiconductor memory device according to claim 12, wherein the film No. 3 is selectively removed. (14) The first conductor film (27) and the second film (28)
) is repeated several times, the opening (29
) The semiconductor memory device according to claim 12, characterized in that the semiconductor memory device is formed with: (15) The first conductor film (27) is connected to the first film (
25) A method for manufacturing a semiconductor memory device according to claim 12, characterized in that the semiconductor memory device is formed directly on the semiconductor memory device. (16) The method of manufacturing a semiconductor memory device according to claim 12, wherein the first and second conductor films (27, 30) are patterned in the same step. (17) The method for manufacturing a semiconductor memory device according to claim 12, wherein the first and second conductor films (27, 30) are patterned in different steps. (18) A pair of impurity diffusion regions (43,
44) and gate electrodes (WL_5, WL_6); and a step of forming an insulating first film (45) covering the transfer transistor (T_3). forming a first opening (47) in the first film (45);
exposing one of the impurity diffusion regions (43, 44), and forming a first conductor film (48) in the first opening (47) and on the first film (45). a step of laminating a second film (49) of a material different from the first film (45) on the first conductor film (48); and a step of laminating a second film (49) on the first conductor film (48), forming a second opening (50) that exposes the first conductor film (48) by removing the second film (49) above; and
A second conductor film (51) inside and on the second film (49).
a step of forming the first and second conductor films (48, 51) and the second film (
49); selectively removing the remaining second film (46) by isotropic etching; A step of forming a dielectric film (52), and a step of forming the dielectric film (52).
2) forming a third conductor film (53) so as to surround the semiconductor memory device. (19) The first film (46) and the first conductor film (48)
), a third film (46) is formed of a material different from the first film (45), and a third film (46) is formed between the first and third films (45, 4).
9) is selectively removed to form the first opening (47), and the remaining second and third films (46, 49) are selectively removed by the isotropic etching. A method for manufacturing a semiconductor memory device according to claim 18. (20) Transfer the first conductor film (48) to the first film (
45) A method for manufacturing a semiconductor memory device according to claim 18, characterized in that the semiconductor memory device is formed directly on the semiconductor memory device. (21) A patent claim characterized in that the steps of forming the second film (46), forming the second opening (50), and forming the second conductive film (51) are repeatedly performed multiple times. 19. A method for manufacturing a semiconductor memory device according to item 18. (22) The method for manufacturing a semiconductor memory device according to claim 18, wherein the first and second conductor films (48, 51) are patterned in the same step. (23) The method for manufacturing a semiconductor memory device according to claim 18, characterized in that the patterning of the first and second conductive films (48, 51) is repeated in a plurality of different steps.