JPH03297166A - Manufacture of semiconductor memory device - Google Patents

Abstract

PURPOSE:To improve the stability of a manufacturing process by forming opening parts in both electrodes of a transistor of an interlayer insulating film and forming a conductive film on the inside of the opening part, and further forming bit lines for terminal connection, a node part, and a storage electrode. CONSTITUTION:Word lines 5 and a MOS transistor(Tr) T using the lines 5 as the gates are formed on a p-type Si substrate 1. A first interlayer insulating film 7 is deposited on the substrate 1 surface an thereafter selectively etched to simultaneously form a bit line contact opening part 8 and a storage electrode contact opening part 9 on source and drain regions of the TrT. Then, bit lines 11 are formed by etching using a mask 10 and are connected to the drain region through the opening 8, and simultaneously a node part 13a is left behind in the opening 9. Further, a storage electrode 13 is formed by etching and is connected to the source region of the TrT through the opening part 9 and via the node part 13a. Hereby, the aspect ratio is lowered and the position accuracy of the bit lines and the node part are improved to permit the stability of the manufacturing process to be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly to a method of manufacturing a stacked DRAM (dynamic random access memory).

<Prior Art> In recent years, the degree of integration of DRAMs has been increasing in order to increase storage capacity, and efforts are being made to reduce the size of memory cells, which are the storage units of DRAMs.

When downsizing a memory cell, the charge storage capacity within the memory cell must be maintained at a certain minimum value in order to prevent soft errors caused by radiation and to ensure a sufficient S/N ratio. For this reason, it has become increasingly difficult to form capacitors for charge storage on the surface of semiconductor substrates, and recently memory devices have been developed in which capacitors are formed inside holes or grooves formed in semiconductor substrates or on MOS transistors on the surface of substrates. The cell (three-dimensional structure memory cell) is formed into a film. Among these, from the point of view of mass production, MOS is used for 4MDRAM and later.
Memory cells in which a capacitor is formed on a transistor (stacked memory cell) are becoming mainstream. Note that memory cells in which capacitors are formed on the inner walls of holes or grooves formed in a substrate are considered difficult to be applied to 64M DRAMs and later because it becomes difficult to separate the capacitors as miniaturization progresses.

At the beginning of the stacked memory cell's development, the capacitor was formed and then the hit line was formed, but recently, as shown in Figures 4(a) and (c), the lower electrode (hereinafter referred to as "storage line") of the capacitor Co is The bit line 18 is formed before the electrode 21 (referred to as "electrode"). As a result, the contact portion 18a of the bit line 18 in the layer of the storage electrode 21
This allows the area of the storage electrode 21 to be expanded to the limit of photolithography. In addition, in Fig. 4, section (b) indicates a planar pattern, and sections (a) and (c) respectively indicate A in section (b).
- A cross section taken along line A and line C-C is shown. Further subdivision (a)
, a cross section taken along line B-B in section (b) is shown with a broken line. When manufacturing this stacked memory cell, specifically, first, an LDD (Lightly Doped Drain) structure MOS transistor T is formed on the surface of a P-type Si substrate 1 to gate the word line 5. In addition, in Figure 4,
2 is an element isolation region made of SiO2, 3 is a gate oxide film, 4 is an etching mask for forming the word line 5, 5iO7, 6 is SiO! which covers the side surfaces of the word line. It shows. For simplicity, the source and drain regions are omitted. Next, a first interlayer insulating film 7 made of S r Ot is deposited to form an opening 8 for a bit line contact, and then a polysilicon film and a 5i02 film are sequentially deposited. After photo-etching the 5rOx film to form a bit line pattern (SIOt17), RIE (reactive ion etching) is performed using 5iOt17 as a mask.
The bit line 18 is formed by processing the polysilicon film using a method. Next, a second interlayer insulating film 1 made of SiOt
9 to form an opening 20 for a storage electrode contact, phosphorus-doped polysilicon is deposited and processed to form a storage electrode 21. And S 1sN4/S i
o t A capacitor C is formed by forming a capacitor insulating film made of a two-layer film and a plate electrode 23 made of phosphorus or arsenic doped polysilicon.

Configure. Note that 24 indicates a third interlayer insulating film made of boron-doped PSG.

<Problems to be Solved by the Invention> However, in the manufacturing method described above, when forming the opening 20 for the storage electrode contact, the two-layer film of the first interlayer insulating film 7 and the second interlayer insulating film 19 is formed. Because the pattern is etched, the aspect ratio (etching depth/pattern width)
There is a problem in that the cost is high and manufacturing is difficult. Also,
This opening 20 is formed in a region surrounded by the word line 5 and the bit line 18, and when the pattern width of the opening 20 increases, the alignment accuracy between the bit line 18 and the node portion 21 of the storage electrode 21 increases. The problem is that it becomes more difficult.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor memory device in which a bit line is formed before a storage electrode, which makes it possible to reduce the aspect ratio when forming an opening for a storage electrode contact. It is an object of the present invention to provide a method for manufacturing a semiconductor memory element that can solve the problem of alignment accuracy between a bit line and a node portion of a storage electrode.

<Means for Solving the Problems> In order to achieve the above object, the method for manufacturing a semiconductor memory element of the present invention includes a transistor formed on the surface of a semiconductor substrate, a transistor formed above the transistor so as to cover the transistor, A method for manufacturing a semiconductor memory element having a storage electrode connected to one terminal of the transistor via a node portion, and a bit line provided between the semiconductor substrate and the storage electrode and connected to the other terminal of the transistor. Then, an interlayer insulating film is deposited on the surface of the substrate after the transistor is formed, and a first . a step of simultaneously forming a second opening on the interlayer insulating film and the first opening; a step of depositing a conductive film within the second opening; forming an insulating film forming a bit line pattern on the conductive film; and selectively etching the conductive film using the insulating film as a mask; forming a bit line connected to the other terminal of the transistor through the second opening, and forming a node portion by leaving the conductive film in the first opening; and forming an insulating film on the substrate. The method comprises the steps of depositing and covering the side surfaces of the bit line with an insulating film by an etch-back method and exposing the surface of the node portion, and forming the storage electrode on the note portion. There is.

<Example> Hereinafter, the method for manufacturing a semiconductor memory element of the present invention will be described with reference to an example.

1 to 3 show a stack type D according to an embodiment of the present invention.
The RAM manufacturing method is shown in the order of steps.

Similarly to Fig. 4, section (b) in each drawing shows a planar pattern, and sections (a) and (c) are cross sections taken along line A-A and line C-C in section (b), respectively. It shows. Furthermore, in section (a), a cross section taken along line B-B in section (b) is shown with a broken line. Further, the same parts as in the conventional example shown in FIG. 4 are indicated by the same reference numerals.

■First, as shown in Figure 1, P-type Si
A word line 5 made of phosphorus-doped polysilicon is formed on the surface of the substrate I, and an LD using this word line 5 as a gate is formed.
MOS) transistor T of D structure is formed. Note that the source area is for simplicity.

The drain region is omitted. Next, on the surface of the substrate l,
The first interlayer insulating film 7 made of 5iOz is deposited by CVD method.
．． Deposit 2 μm. followed by photolithography and R
The first interlayer insulating film 7 is selectively etched using the IE method to form openings 8. for bit line contacts at locations corresponding to the source and drain regions of the MOS transistor T, respectively. An opening 9 for a storage electrode contact is formed at the same time. Since both openings 8.9 are formed simultaneously, alignment accuracy between both openings 8.9 is not a problem. Furthermore, since only one layer of the first interlayer insulating film 7 is etched, the aspect ratio is lower than that of the conventional method. Therefore, both openings 8.9 can be easily formed.

■Next, the bit line 1 is
Polysilicon is deposited to a thickness of 0.1 .mu.m over the entire surface as a material for the first layer constituting No. 1, and 5iOy is further deposited by 200 layers over the entire surface as a protective film for ion implantation. Subsequently, arsenic is ion-implanted into the polysilicon to form N+ type polysilicon, and the ion-implanted protective film 5iOz is removed by wet etching.

■Next, using the CVD method, 0.1 μm of W Sit was deposited on the entire surface as the second layer material constituting the bit line 1, and 2 μm of 5iOz was further deposited on the entire surface as the material for the mask IO.
Deposit m.

(2) Next, this 5ins is processed by photolithography and RIE to form a mask 10 having a pattern of a bit line 11. Then, by RIE method, the mask lO
The bit line 11 made of two layers of WSiz and N'' type polysilicon (hereinafter referred to as "W polycide") is formed by etching the WSiz and N'' type polysilicon in the area not covered by the etching process. do. This makes bit 4
1jllll is connected to the drain region of the transistor T from above the first interlayer insulating film 7 through the opening 8 for bit line contact. At this time, W polycide (
The node portion) 13a remains in the opening 9 for the storage electrode contact. Therefore, the bit line 11 and the node portion 13
a can be formed into a self-line.

■Next, using the CVD method, SiOt is deposited on the entire surface as a material for the sidewall 12 that covers the side surface of the bit line 11.
．． Deposit 2 μm. Subsequently, RIE is performed and the SiOx is processed by an etching method to form the sidewall 12. As a result, the bit line 11 is surrounded by the first interlayer insulating film 7. It is in a state of being wrapped by the mask IO and the sidewall 12, and is electrically insulated. Also, at this point, the 5 ift deposited on the W polycide 13a is completely etched, leaving the surface of the W polycide 13a exposed.

Next, as shown in FIG. 3, polysilicon is deposited to a thickness of 0.5 μm over the entire surface as a material for the storage electrode 13 using the CVD method, and then Sin is deposited over the entire surface as a mask material for etching this polysilicon. A thickness of 0.1 μm is deposited on the surface. Then, this SiO2 is processed by photolithography and RIE to form a mask forming the pattern of storage electrode 13, and then the polysilicon is etched by RIE to form storage electrode 13. continue,
POC (PSGC phosphorus glass by oxidation using 2s gas) is formed, and phosphorus is introduced from this PSG into the storage electrode 13 to form N+ type polysilicon. At this point, the storage electrode 13 is connected to the node portion 13a and to the source region of the transistor T via this node portion 13a. Therefore, unlike conventional manufacturing methods, there is no need to form an opening with a high aspect ratio.
The storage electrode 13 can be connected to the source region of the transistor T through the opening 9 formed in .

■Next, as in the conventional example, wet etching is performed to remove the PSG, and then 5ISN4 is deposited by CVD and oxidized to form S 13N4/S 10 t2.
Capacitor insulating film consisting of a layered film (thickness 5 in terms of SiOz)
0 people) form 14. Subsequently, polysilicon was deposited to a thickness of 0.2 μm as a material for the plate electrode 15 using the CVD method, and phosphorus was introduced in the same manner as for the storage electrode 13 to form an N"
The mold is made of polysilicon.

After removing PSG generated during phosphorus introduction, this N4 type polysilicon is processed by photolithography and RIE to form a plate electrode I5. Storage electrode 13. Insulating film 14 and plate electrode 15 constitute capacitor CI.

Finally, a second interlayer insulating film 16 made of boron-doped PSG is deposited by the CVD method, and the second interlayer insulating film 16 is planarized (melted) by annealing in a nitrogen atmosphere.

In this way, in this method of manufacturing a stacked DRAM, when forming the storage electrode contact opening 9 by etching, it is possible to form the storage electrode contact with a lower aspect ratio than the conventional method. Moreover, the bit line 11 and the node portion 13a can be formed as a self-aligned line, and therefore the problem of alignment accuracy between the bit line 11 and the node portion 13a can be solved. Therefore, the stability of the manufacturing process can be improved.

<Effects of the Invention> As is clear from the above, according to the method of manufacturing a semiconductor memory element of the present invention, the aspect ratio can be lowered when forming an opening for a storage electrode contact. Furthermore, the bit line and the node portion of the storage electrode can be formed in a self-aligned line, and the problem of alignment accuracy between the bit line and the node portion can be solved. therefore,
The stability of the manufacturing process can be improved.

[Brief explanation of the drawing]

1 to 3 are process diagrams illustrating a method for manufacturing a DRAM according to an embodiment of the present invention, and FIG. 4 is a diagram showing a DRAM manufactured by a conventional manufacturing method. ■...P-type silicon substrate, 2...Element isolation region, 3
・・・Gate oxide film, 4.6...S iOt s5・
... Word line, 7... First interlayer insulating film, 8... Opening for bit line contact, 9... Opening for storage electrode contact, IO... Mask, II... Bit line, 12... side wall, 13... storage electrode, 1
3a... Node part, 14... Capacitor insulating film, 1
5... Plate electrode, 16... Second interlayer insulating film.

Claims (1)

[Claims] (1) A transistor formed on the surface of a semiconductor substrate,
A storage electrode formed above the transistor so as to cover it and connected to one terminal of the transistor via a node portion, and a bit provided between the semiconductor substrate and the storage electrode and connected to the other terminal of the transistor. A method for manufacturing a semiconductor memory element having a wire, the method comprising: depositing an interlayer insulating film on the surface of the substrate after forming the transistor; a step of simultaneously forming an opening in the first and second openings; a step of depositing a conductive film on the interlayer insulating film and in the first and second openings; and forming an insulating film in a bit line pattern on the conductive film. The conductive film is selectively etched using the insulating film as a mask to form a bit line connected to the other terminal of the transistor through the second opening, and the conductive film is etched inside the first opening. a step of depositing an insulating film on the substrate and using an etch-back method to cover the sides of the bit line with the insulating film and exposing the surface of the node part; A method of manufacturing a semiconductor memory element, comprising the step of forming the storage electrode on the node portion.