JPH01140851U - - Google Patents
Info
- Publication number
- JPH01140851U JPH01140851U JP1988036533U JP3653388U JPH01140851U JP H01140851 U JPH01140851 U JP H01140851U JP 1988036533 U JP1988036533 U JP 1988036533U JP 3653388 U JP3653388 U JP 3653388U JP H01140851 U JPH01140851 U JP H01140851U
- Authority
- JP
- Japan
- Prior art keywords
- variable capacitance
- semiconductor variable
- lead terminals
- cathode
- capacitance device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 6
- 239000008188 pellet Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Semiconductor Integrated Circuits (AREA)
Description
第1図及び第2図は夫々本考案を説明する為の
平面図である。 1は複数個のバリキヤツプ2を形成した半導体
ペレツト、3はアイランド、4はアノード端子、
5はカソード端子である。
平面図である。 1は複数個のバリキヤツプ2を形成した半導体
ペレツト、3はアイランド、4はアノード端子、
5はカソード端子である。
Claims (1)
- 【実用新案登録請求の範囲】 (1) アイランド上に複数の半導体可変容量素子
を載置した半導体可変容量装置において、隣接す
るアノード(カソード)用リード端子の間にカソ
ード(アノード)用リード端子を配置するように
リード端子群を配列したことを特徴とする半導体
可変容量装置。 (2) 前記半導体可変容量素子は3又は4個であ
ることを特徴とする半導体可変容量装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1988036533U JPH01140851U (ja) | 1988-03-18 | 1988-03-18 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1988036533U JPH01140851U (ja) | 1988-03-18 | 1988-03-18 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01140851U true JPH01140851U (ja) | 1989-09-27 |
Family
ID=31263131
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1988036533U Pending JPH01140851U (ja) | 1988-03-18 | 1988-03-18 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01140851U (ja) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5247310A (en) * | 1975-10-14 | 1977-04-15 | Sony Corp | Double super receiver |
-
1988
- 1988-03-18 JP JP1988036533U patent/JPH01140851U/ja active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5247310A (en) * | 1975-10-14 | 1977-04-15 | Sony Corp | Double super receiver |