JPH01140816A - Synchronizing circuit for viterbi decoder - Google Patents

Abstract

PURPOSE:To reduce data to be lost by resetting all state metric circuits which have random values and which are in respective state to a specific value. CONSTITUTION:When one time synchronous information are accumulated and the segment of data detects an asynchronous state in the synchronous detecting circuit 6 of a code, a reset pulse generating circuit 21 generates a reset pulse for making the state metric circuits in all states which a viterbi decoder can take to '0' with respect to a state metric storage circuit 5. As a result, the state metric circuits in all states become equal, and respective sate metric circuits speedily reach a steady state, whereby the ACS(addition, comparison and selection) circuit 4 of the viterbi decoder can speedily begin a normal action. When the viterbi decoder changes the segment of data and is set in the synchronous state after the asynchronous state, the error of decoded data can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synchronization circuit for a Viterbi decoder, which is one of the error correction methods in digital communication.

[Conventional technology]

Figure 2 is a block diagram showing the synchronization circuit of a conventional Viterbi decoder. In the figure, (1) is an input terminal for input encoded data to the Viterbi decoder, and (2) is a phase control that controls the delimitation of encoded data. circuit, (31 is a branch metric calculation circuit, (4) is an AC3 <addition/comparison/selection] circuit, (5) is a state metric storage circuit, (6) is a code synchronization detection circuit, (7) is a path memory circuit , (8) are output terminals for error-corrected decoded data.

Next, the operation will be explained. The Viterbi decoder is a method for decoding convolutional codes, and normal decoding cannot be performed unless the delimiter of convolutionally encoded data on the transmitting side and the delimiter of data decoded on the receiving side match. The phase control circuit (2) in FIG. 2 is a circuit that adjusts such data delimitation, and changes the data delimitation when the code synchronization detection circuit (6) detects non-synchronization.

Such changes in data delimitation are performed in the synchronization detection circuit (6) until synchronization is detected. the result,
The data delimiters in transmission and reception match, and a normal Viterbi decoder consisting of a branch metric calculation circuit (3), an AC5 circuit (48 step metric storage circuit (5), and a path memory circuit (7)) Decoding is performed.The code synchronization detection circuit (6) detects code synchronization/decoding.
Various types of information have been proposed for use in detecting asynchrony; for example, there is a method that utilizes the fact that the state metric increases at different rates during synchronization and asynchronous times (References: Yasuda, Hirata; "Study on code synchronization method in Viterbi decoding"; Institute of Electronics and Communication Engineers Communication System Study Group C682-43P, 17) [Problems to be solved by the invention] The synchronization circuit of the conventional Viterbi decoder is configured as described above. Therefore, if the Viterbi decoder falls into an asynchronous state for some reason, the contents of the state metric storage circuit will become a random value in the asynchronous state, so even if the Viterbi decoder goes from an asynchronous state to a synchronous state again, There is a problem in that a large portion of the data after the transition to the state is lost.

This invention was made to solve the above-mentioned problems, and aims to reduce as much data as possible even after transition to a synchronized state.

[Means for solving problems]

When the synchronous circuit of the Viterbi decoder according to the present invention detects that it is in an asynchronous state and changes the delimiter of the input encoded data, it resets all the contents of the state metric storage circuit and changes the state of each state of the Viterbi decoder. All state metric values are set to constant values, and the subsequent decoding operation is performed.

[Effect]

In other words, by resetting all the state metrics of each state that had random values to constant values, the Viterbi decoder can perform normal decoding operations, and as a result, decoded data that is lost due to errors can be reduced. This is to reduce the number.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 2υ is a code synchronization detection circuit (6) that detects asynchrony and delimits data using a phase control circuit (2).
When changing the state metric storage circuit (5
) is a reset pulse generation circuit that generates a reset pulse for

Next, the operation will be explained. In FIG. 1, the code synchronization detection circuit (6) detects that the data delimiter is in an asynchronous state as a result of integrating certain time synchronization information.
At this time, the reset pulse generation circuit 3 generates a reset pulse for the state metric storage circuit (5th ζ) to set the state metrics of all possible states of the Viterbi decoder to O. As a result, all states Since the state metrics of each state metric have the same value and each state metric quickly reaches a steady state, the AC8 circuit (4) of the Viterbi decoder can quickly enter normal operation.

Therefore, when the Viterbi decoder enters a synchronized state by changing the data delimiter after being in an asynchronous state, errors in decoded data can be reduced.

〔Effect of the invention〕

As described above, according to the present invention, the state metrics of all states are reset immediately after the Viterbi decoder detects that it is in an asynchronous state, so there is an effect that decoded data with fewer errors can be obtained. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a synchronization circuit of a Viterbi decoder according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a synchronization circuit of a conventional Viterbi decoder. In the figure, (6) indicates the synchronization detection circuit, and (2) indicates the reset pulse generation circuit. In the figure, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] synchronization detection means for detecting the synchronization/asynchronous state of the code of the Viterbi decoder; and when the asynchronous state of the synchronization detection means is detected, state metric values of all states in the state metric storage circuit in the Viterbi decoder; A synchronization circuit for a Viterbi decoder, comprising a reset means for resetting the values to the same value.