JP3135786B2 - FM multiplex broadcast receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an FM multiplex broadcasting receiver, and more particularly, to a transmission and broadcasting system using a transmission format in which interleaved horizontal blocks forming a cyclic code are regarded as a product code frame. , FM multiplex broadcast receiver.

[0002]

2. Description of the Related Art In mobile FM multiplex broadcasting, as shown in FIG. 9, one frame of data is composed of a plurality of blocks. As is commonly seen, a synchronization signal (framing code) is provided only at the beginning of a frame. Instead, four types of BICs (Block Identification Codes) acting as synchronization signals are added to the head of each packet. Therefore, the mobile FM multiplex broadcast receiver obtains block synchronization by detecting the BIC, and obtains frame synchronization by detecting a change point of the block identification code. That is, there are four types of BICs, BIC1 to BIC4, and BIC4 → BIC1, BIC1 → BIC3, BIC during one frame.
There are four changing points, such as 4 → BIC2 and BIC2 → BIC3, which can determine the position in the frame. In the conventional frame synchronization reproducing circuit, if the BIC change pattern matches this frame change point, frame synchronization has been established. That is, frame synchronization is established by detecting a frame change point.

[0003]

In such prior art, since frame synchronization is determined only by the BIC, the frame synchronization cannot be determined when the BIC cannot be detected at the frame change point, and therefore, the frame synchronization is determined. It took time. Therefore, a main object of the present invention is to provide an FM multiplex broadcast receiver capable of detecting frame synchronization at high speed.

[0004]

According to a first aspect of the present invention, an FM multiplex broadcasting receiver for interleaving horizontal blocks of a cyclic code and receiving data in which a frame of a product code is formed includes the steps of: longitudinal error correction unit performs longitudinal error correction on the data obtained by solving the interleaving regarded as tentative first block of the frame, the vertical error correction
Counting means for counting the number of successes, the number of successes is a predetermined number or more
In the case of, the temporary head block is replaced with the head block of the true frame.
Frame synchronization to establish frame synchronization
Means, and the data received during vertical error correction.
Block that detects whether block synchronization is lost
When the block is out of synchronization
Even if the vertical error correction succeeds more than
The system synchronization establishing means does not establish frame synchronization, and is an FM multiplex broadcast receiver.

[0005] A second invention is directed to a block of a cyclic code in a horizontal direction.
Are interleaved to form a product code frame.
In a FM multiplex broadcast receiver that receives
The block is regarded as the temporary head block of the frame and
Vertical error correction for data that has been solved
Directional error correction means, utilizing the vertical error correction result
Frame synchronization forward protection means to be reset, and BI
C Frame that performs frame synchronous playback by detecting a change point
And a frame synchronization forward protection means,
Just reset by the frame synchronous playback means
And resetting using the result of the vertical error correction means.
An FM multiplex broadcast receiver characterized in that

[0006]

According to the first aspect of the present invention, when the frame synchronization is not determined, one horizontal block is regarded as a temporary head block of the frame, and the vertical error correction is performed a plurality of times by the vertical error correction means on the interleaved data. Do. The counting means counts the number of successful vertical error corrections, and only when the number of successful times indicates a predetermined number or more, the frame synchronization establishing means establishes frame synchronization by regarding the temporary block as a head block of a true frame. I do. If the continuity monitoring means detects that the block synchronization is lost within one frame, the vertical error correction is not executed, and the data received during the vertical error correction by the block synchronization reproducing means is not transmitted. Is detected, the frame synchronization is not established by the frame synchronization establishing means, even if the vertical error correcting means has succeeded a predetermined number of times or more by the vertical error correcting means. This prevents establishment of frame synchronization at an incorrect position.

Further, a conventional frame synchronization reproducing means for performing frame synchronization reproduction based on the change point of the BIC may be used together. In this case, the frame synchronization determination operation performed when the frame synchronization is not determined is performed by the frame synchronization reproduction means. Alternatively, the result of the frame synchronization establishing means which has established the frame synchronization earlier is used. In the second invention, the continuation of the frame synchronization period is extended by resetting the frame synchronization forward protection circuit even when the counting means detects that the vertical error correction has succeeded a predetermined number of times or more when the frame synchronization is determined.

[0008]

According to the present invention, frame synchronization can be detected at high speed and with high accuracy, and the continuation of the frame synchronization period can be extended. Therefore, it is inevitable that more data packets and parity packets can be classified quickly and reliably, and the time required for providing received data to the user can be reduced.

The above objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In a transmission format in which interleaved horizontal blocks constituting a cyclic code are regarded as a product code frame, if the interleave is solved starting from a point different from the true starting point as the starting point of the frame, , It is generally difficult to decode the true codeword. However, as in the case where error correction for random data may be successful, when error correction in the vertical direction is performed on a bit sequence in which interleaving is incorrectly configured, error correction may be successful. Therefore, in the present invention in which frame synchronization is achieved by using the vertical error correction result, the vertical error correction performed by assuming one block as a temporary head block of the frame is performed a predetermined number of times as in the embodiment described below. Only when the above succeeds, the provisional head block is regarded as the head block of the true frame.

In the mobile FM multiplex broadcast, one product-coded frame is formed by interleaving parity blocks between coded data blocks (see FIG. 9). It is difficult to decode the true codeword if the interleave is solved starting from a point different from the starting point of That is, (272,
190) Since the shortened difference set cyclic code has the property of a cyclic code, that is, has the property of rotating one code word into another code word, the frame of mobile FM multiplex broadcasting Data packet 1 without structure interleaving
１９０190 and the parity packets 1８２82 are arranged in this order, even if the starting point of the frame is shifted by one block in the transmission direction, the decoding range of another codeword becomes (with a probability of １ ／, this codeword is 272). Only the bit is wrong.) However, the interleaving rule used for the mobile FM multiplex broadcasting also takes this point into consideration as shown in FIG. 9, and if the starting point of the deinterleaving frame is slightly wrong, the BI
It is determined that the vertical position of C does not substantially coincide with the vertical position of the BIC from the true start point (see FIG. 8). Therefore, if the starting point of the frame for performing the deinterleaving is mistaken, the vertical error correction rarely succeeds, and there is a possibility that the frame synchronization can be established using the vertical error correction result. In addition, FIG.
When deinterleaving is performed by shifting the starting point of one frame for performing deinterleaving, a group in which the relative order of the blocks in the same frame is preserved (for example, shifted by +1 block from the original block position) The number of blocks included in the group including the largest number of blocks,
This is shown according to each shift amount.

As is apparent from FIG. 8, when the shift amount is 0 block, decoding is possible because all of the 272 bits in the vertical direction match, but interleaving is performed starting from a point shifted by one block in the transmission direction. Is solved, the maximum number of blocks having the same relative order is 108 blocks, so that decoding when shifted is generally more difficult than decoding when the starting point is not mistaken. Therefore,
It is considered that the vertical error correction is performed on each column of the deinterleaved data starting from the temporary frame, and the frame synchronization can be determined by performing the vertical error correction successfully a plurality of times.

According to this method, the influence of an overlooked error in synchronizing frames using the result of vertical error correction can be eliminated on condition that the vertical error correction succeeds a plurality of times. In addition, the continuity of block synchronization must be considered. For example, once the block synchronization for the horizontal block is lost within the frame,
This is a case where vertical error correction is performed on a frame constituted by blocks newly established by block synchronization.
In this case, if the second half of the block synchronization is incorrectly determined and if the number of blocks after the incorrect block synchronization is determined is about several blocks, there is a possibility that the vertical error correction is successful and the wrong frame synchronization is established. is there. The simplest way to avoid this phenomenon is to perform vertical error correction when frame synchronization is not determined if block synchronization is not lost within one frame and block synchronization is lost at the first block of the next frame. The present invention employs a technique that does not establish frame synchronization even if vertical error correction is successful in a plurality of bit strings.

FIG. 1 shows an FM multiplex broadcast receiver 10 according to one embodiment of the present invention. In the following description, it is assumed that block synchronization has already been achieved. FM multiplex broadcast receiver 1
0 includes terminals 12 and 14. Terminals 12 and 14 are supplied with received data a of the mobile FM multiplex broadcast reproduced by a demodulator (not shown) and a clock signal b of the FM multiplex broadcast synchronized with the received data a, respectively.
The data transfer rate of the received data a is, for example, 16 kbp
s. Then, the received data a and the clock signal b
Are used for block synchronous reproduction and frame synchronous reproduction by a synchronous reproduction method using a BIC in the synchronous reproduction circuit 16. The synchronous reproduction circuit 16 is configured, for example, as shown in FIG.

The synchronous reproduction circuit 16 shown in FIG. 2 includes a BIC detection circuit 18, and the BIC detection circuit 18 determines whether or not the input received data a is within the BIC error allowable bit number. If the pattern is within the BIC error allowable bit number, the BIC detection circuit 18 determines which BIC the received data a is. That is, the BIC detection circuit 18 determines that the received data a is BIC1, BIC2, BI
It is determined which of C3, BIC4 and BIC could not be detected, and the result is used as a 3-bit BIC status signal c, for example, as a frame synchronization reproduction circuit 1.
9 is output to the BIC status register 20 included in FIG. BI
C state register 20 includes, for example, a two-stage shift register.

The counter 22 is a modulo 288 counter that counts up in synchronization with the clock signal b. Therefore, the counter 22 counts the number of bits (0 to 287) forming one block by the clock signal b input from the terminal 14, and outputs the shift and latch signal d each time the BIC detection position comes. In addition,
The counter 22 is reset by a reset signal from the block synchronous reproduction circuit 66. BIC indicated by shift and latch signal d from counter 22
At the time of detection, each stage of the BIC status register 20 shifts to the right, and simultaneously the BIC from the BIC detection circuit 18
The status signal c is latched at the first stage of the BIC status register 20. Therefore, the signal output from each stage of the BIC status register 20 indicates what BI
Indicates whether C has been detected, that is, indicates the BIC pattern.

The BIC pattern determination circuit 24 to which the BIC pattern from the BIC status register 20 is provided is constituted by, for example, a ROM. The BIC pattern included in Table 1 is stored in the BIC determination circuit 24, and is regarded as a normal change pattern.

[0018]

[Table 1]

In Table 1, t is the current time and t−2.
Reference numeral 88 denotes a block one block before, and the output address indicates an address output when each BIC pattern is detected. BIC
The output from the first and second stages of the status register 20, that is, the BIC pattern is stored in the BIC pattern determination circuit 24 as shown in Table 1.
Is compared with the BIC pattern included in the. BI containing the BIC pattern from BIC status register 20 in Table 1
If the BIC pattern determination circuit 24 detects that the pattern is a C pattern, that is, if the given BIC pattern is a pattern indicating a frame change point (hereinafter, simply referred to as a “frame change pattern”), the detection signal e and the detected pattern And an address f as shown in Table 1 corresponding to.

When the frame is not synchronized, the output of the Q terminal of the JK-FF 26 goes high, and every time a BIC is detected, the load signal is sent to the frame counter 32 via the AND circuit 28 and the OR circuit 30. Output g. When the high-level load signal g is supplied to the frame counter 32, the frame counter 3
2 is loaded with the address f via the selector 34.

As described above, when the frame change point is detected and the frame synchronization acquisition operation is started, the frame counter 32
To the comparator 36. Address f
The comparator 36 outputs a high-level signal each time the value matches the frame change point detection address stored in the comparator 36 in advance. As long as the BIC pattern determination circuit 24 continuously detects the frame change pattern at the timing when the output of the comparator 36 becomes high level, the NOT circuits 38, 40, the AND circuits 42 and 44 use the counter 46 for the frame synchronization backward protection. Is counted up. Then, when the counter 46 reaches a predetermined frame synchronization backward protection count, the output from the RCO terminal changes from low level to high level, and the high level signal is given to the JK-FF 26 via the OR circuit 48. And
The output from the Q terminal of the JK-FF 26 is set to a high level. This establishes frame synchronization.

The counter 50 for frame synchronization forward protection operates when frame synchronization is established by the AND circuit 52. That is, if the BIC pattern determination circuit 24 fails to detect the frame change pattern, despite the fact that the frame counter 32 indicates the frame change point detection position when the frame synchronization is established, the AND circuit 5
The output of 2 becomes high level, and the counter 50 is operated. Therefore, if the BIC pattern determination circuit 24 cannot detect the frame change pattern at the regular timing indicated by the frame counter 32,
The counter counts up in accordance with the high level output from the D circuit 52, and if it is detected, the high level output from the AND circuit 54 is output to the CL of the counter 50 via the OR circuit 58.
The counter 50 is provided to the R terminal and reset. If the value of the counter 50 has reached a predetermined number of frame synchronization forward protections, the JK-
A high-level signal is output to the K terminal of the FF 26, and the frame synchronization signal output from the Q terminal, that is, the terminal 58 becomes low level, and the frame synchronization is lost.

Further, by adding components as described below, more accurate acquisition of frame synchronization is realized. That is, the signal h from the successful correction count circuit 77 is input from the terminal 60. When frame synchronization is established, a high-level signal is input to the OR circuit 62 from the Q terminal of the JK-FF 26, so that the output of the OR circuit 62 becomes high. Only when the output of the OR circuit 62 is at a high level, the AND circuit 64
Depends on the signal h. That is, when the output of the OR circuit 62 is at a high level, the high-level signal h
The counter 50 via the ND circuit 64 and the OR circuit 56
, The counter 50 for the frame synchronization forward protection circuit is reset.

When the frame synchronization is not established, the signal h becomes valid only when the block synchronization signal (high level when the block synchronization is established) output from the block synchronization reproducing circuit 66 is at a high level. Note that the block synchronization reproducing circuit 66 generates a block synchronization signal based on the BIC state signal c and the shift and latch signal d. Here, the reason that the block synchronization signal and the signal h are ANDed by the AND circuit 64 is that when the block synchronization is lost at the beginning of the frame and a new block synchronization acquisition operation is performed, the frame synchronization position where the angle is determined is incorrect. This is because there is a possibility. That is, if the frame synchronization is established by the signal h while the block synchronization is not established, erroneous synchronization may occur. Therefore, when the block synchronization of the received data a is out of synchronization during the vertical error correction, the frame synchronization is not established even if the vertical error correction succeeds a predetermined number of times or more and the high-level signal h is output.

On the other hand, when the block synchronization is established, the high-level signal h is supplied to the selector 3 via the AND circuit 64.
4 given. Then, the selector 34 always outputs “1”.
Is output to the frame counter 32 as an address. The signal h is also used as a load signal g of the frame counter 32 via the OR circuit 30. At the same time, the signal h sets the JK-FF 26 through the OR circuit 48 to determine the frame synchronization. That is, when the number of successful vertical error corrections is equal to or greater than a predetermined number, the temporary head block is regarded as the head block of a true frame, and frame synchronization is established.

Therefore, when the frame synchronization is not determined,
Of the high-level output from the RCO terminal of the counter 46 or the high-level signal h, the JK-FF
The frame synchronization is determined by the signal given to. When the frame synchronization is determined, the counter 50 for the frame front protection circuit is reset by either the high-level output from the AND circuit 54 or the high-level signal h when the block synchronization is determined. Further, if the block synchronization is lost when the frame synchronization is not determined, the frame synchronization is not established even if the high-level signal h is output.

The latch and shift signal d from the counter 22 is applied to a memory counter 68. The memory counter 68 is counted up by the latch and shift signal d, and generates a row address (vertical address) of the data memory 70. Also, the counter 22
Generates a column address (lateral address) of the data memory 70 based on the clock signal b.

Returning to FIG. 1, such a synchronous reproduction circuit 1
6 outputs the address i (row address + column address) to the data memory 70. The address i is used to save the received data a in the data memory 70 based on the detected synchronization information j. As shown in FIG. 3, in the data memory 70, an address at which the reception data a is written to the data memory 70 by block synchronization is set in the horizontal address. In the horizontal address, “0” for BIC is used.
15 ”, and“ 16 ”for the (272, 190) code.
To 287 "and" 288 to 288 "for synchronization information.
303 ". The vertical address is determined in the order of blocks delimited by block synchronization, that is, the transmission order. In this case, "0- (MAX-
1) is included. The data memory 70
The synchronous information j written in the block includes the fixed state of each of the block synchronization and the frame synchronization of the synchronous reproduction circuit 16,
The value of the frame counter 32 in the synchronous reproduction circuit 16 is included. Note that a circuit for adding the PN code fixed to the (272, 190) code section of the horizontal block in the mobile FM multiplex broadcast is omitted in FIG. 1 to avoid complication of the drawing.

If frame synchronization is determined based on the received data a written in the data memory 70 in this way, horizontal error correction is performed, and the remaining time of one block is transmitted. The vertical error correction and the horizontal error correction after the vertical error correction are performed using
In the case where the frame synchronization has not been determined, conventionally only horizontal error correction is substantially performed. However, in this embodiment, even when the frame synchronization is not determined, the vertical error correction is performed by the following method.

That is, when the timing generation circuit 72 receives the signal k indicating the break between blocks input from the synchronous reproduction circuit 16, the timing generation circuit 72 performs the processing based on the address A of the data memory 70 in which the received data a is written at that time. , The tentative start (head) block of the frame is determined. That is, assuming that the maximum number of blocks accommodated in the data memory 70 is MAX, the temporary start block is determined by Equation 1.

[0031]

## EQU1 ## Temporary start block = Mod (vertical address value of address A-273, MAX) where 272 <MAX where Mod (x, y) represents the value of x when y is modulo. . It should be noted that subtracting 273 not “272” but “1” more than that from the vertical address value that is a part of the address A is performed when the vertical address is counted “1” when the timing generation circuit 72 receives the signal k. Because it has been up.

The timing generation circuit 72 generates an address 1 obtained by combining a vertical address obtained by deinterleaving the temporary start block and a designated horizontal address.
(FIG. 6B) is generated and (27)
(2,190) The designated bit m in the code is read over 272 blocks and loaded into the error correction circuit 74 and the continuity monitoring circuit 76. Then, the horizontal error correction is completed, and the horizontal error correction end signal t (FIG. 6A)
Is output from the timing generation circuit 72 to the D-FF 78 in the continuity monitoring circuit 76 shown in FIG.
, And the D-FF 78 is set to “0”. D
Each time the signal o indicating the establishment state of the block synchronization, which is “1” when the block synchronization is determined and becomes “0” when the block synchronization is not determined, is read out from the data memory 70 in accordance with the signal p (FIG. 6C). latch o. That is, the continuity monitoring circuit 76 outputs “1” to the signal o during one frame period.
To see if is standing. If the signal "0" on the way
When the data is entered, the data may be different or the block may be missing, so that such data and state are avoided to prevent erroneous synchronization from being established. Note that the continuity monitoring circuit 76 sets the D-level when at least one “0” indicating indefinite is present among the 272 signals o indicating the block synchronization establishment state in one frame.
The signal q (FIG. 6E) from the FF 78 is "1" until the end.
The configuration is such that a NOT circuit 80 and an OR circuit 82 are added. In FIG. 6, the output from the OR circuit 82 is as shown in FIG.

When the frame synchronization is not determined, the block synchronization establishment state is checked over one frame. During that time, if the signal q of the D-FF 78 is "0", the vertical error correction can be executed. "1" during inspection of one frame
When the signal g is output, the vertical error correction is not executed. That is, the timing generation circuit 72 that has detected that the signal q is “0” sends a data load (start of decoding) signal r to the error correction circuit 74 and (272,
190) A signal s is sent which instructs the error correction circuit 74 to load a given bit in the code into the error correction circuit 74 over 272 blocks and to execute a series of vertical error correction.

When the vertical error correction is completed, the error correction circuit 74 outputs a correction end signal t to the timing generation circuit 72. Therefore, the signal s for executing the vertical error correction is sent from the timing generation circuit 72 to the error correction circuit 74 as long as the time until the next horizontal error correction is allowed. Further, the error correction success number counting circuit 84 outputs a correction end signal t (FIG. 7) from the error correction circuit 74.
(E)) and the vertical error correction result signal u (“0” at the time of successful correction: FIG. 7 (F)). The error correction success number counting circuit 84 counts the correction result signal u.
The successful correction count circuit 84 includes a counter 86 as shown in FIG. The counter 86 outputs a signal v (“0” at the time of horizontal error correction) indicating whether horizontal error correction or vertical error correction output from the timing generation circuit 72.
(D)) as a clear signal, a correction end signal t of the error correction circuit 74 as a clock signal, and a correction result signal u (correction failure “0”) as an enable.

The AND circuit 88 and the NOT circuit 9
0 is provided to hold the counter 86 when the number of successful vertical error corrections is equal to or greater than a predetermined number. Here, the predetermined number depends on the success probability of the vertical error correction. The success probability may be, for example, 60% or more. Therefore, depending on the operation clock, if the vertical error correction is performed 30 times, the predetermined number is set to about 20 times.

When the count (FIG. 7 (G)) of the error correction success count circuit 84 reaches a predetermined number, the signal h is output.
(FIG. 7H) changes from “0” to “1”, and changes the frame synchronization state from the undetermined state to the determined state only when the synchronization reproduction circuit 16 continues the block synchronization determined state (FIG. 7 (H)). 7 (I)). FIG. 7A shows the signal j, and FIG.
7B shows a vertical address in the address A, and FIG. 7C shows an operation state. "H" in the operating status indicates horizontal error correction,
“V” indicates vertical error correction, and “R” indicates a block synchronization continuity monitoring operation.

The FM multiplex broadcast receiver 10 configured as described above can be used even when frame synchronization is determined.
When the error correction in the vertical direction succeeds a predetermined number of times or more, the counter 50 for the front protection circuit in the synchronous reproduction circuit 16 is reset, so that the frame synchronization determination state can be continued. In this embodiment, when the frame synchronization is determined, the horizontal error correction is performed as in the conventional case, and the vertical error correction and the horizontal error correction after the vertical error correction are performed using the remaining time in one block. If error correction is performed and frame synchronization is not determined, the conventional circuit performs vertical error correction unlike the conventional circuit in which only horizontal error correction is substantially performed. Operation rate can be improved.

Further, in this embodiment, not only the BIC but also the error correction applied in the vertical direction of the frame can be used to reproduce the frame synchronization with higher speed and higher accuracy.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating an example of a synchronous reproduction circuit.

FIG. 3 is an illustrative view showing a configuration of a data memory;

FIG. 4 is a circuit diagram illustrating an example of a continuity monitoring circuit.

FIG. 5 is a circuit diagram illustrating an example of an error correction success number counting circuit.

FIG. 6 is a timing chart showing a block synchronization continuity monitoring operation.

FIG. 7 is a timing chart showing a frame synchronization establishing operation.

FIG. 8 is a graph showing the number of matches of the BIC type with respect to the block shift amount.

FIG. 9 is an illustrative view showing a frame structure of a mobile FM multiplex broadcast;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... FM multiplex broadcast receiver 16 ... Synchronous reproduction circuit 70 ... Data memory 72 ... Timing generation circuit 74 ... Error correction circuit 76 ... Continuity monitoring circuit 84 ... Error correction success count circuit

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Toru Kuroda 1-10-11 Kinuta, Setagaya-ku, Tokyo Inside Japan Broadcasting Corporation Broadcasting Research Institute (72) Inventor Masayuki Takada 1-110-11 Kinuta, Setagaya-ku, Tokyo Japan Broadcasting Corporation Broadcasting Research Institute (72) Inventor Tadashi Isobe 1-10-11 Kinuta, Setagaya-ku, Tokyo Japan Broadcasting Corporation Broadcasting Research Institute (72) Inventor Tsutomu Yamada 1-110 Kinuta, Setagaya-ku, Tokyo Japan Broadcasting Corporation Japan Broadcasting Research Institute (56) References JP-A-5-268212 (JP, A) JP-A-62-253039 (JP, A) JP-A-63-1128 (JP, A) JP-A-63-163 226147 (JP, A) JP-A-2-58943 (JP, A) JP-A-5-252128 (JP, A) JP-A-5-268211 (JP, A) JP-A-5-145500 (JP, A) JP-A-6-125341 (J (P, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H04L 1/00 H03M 13/00 H04J 3/00 H04L 7/00

Claims (4)

(57) [Claims] 1. An FM multiplex broadcasting receiver for receiving data in which a product code frame is formed by interleaving horizontal blocks of a cyclic code, wherein a certain horizontal block is regarded as a temporary head block of the frame and interleaved. longitudinal error correction means for performing a longitudinal error correction on the solved data, the longitudinal error counting means for counting the number of successful correction, the head blow the temporary if the number of successes is equal to or more than a predetermined number of times
Frame as the first block of the true frame
Frame synchronization establishment means for establishing synchronization, and vertical error
Block synchronization of the data received during
Block synchronization reproducing means for detecting whether or not the block is out of synchronization.
Frame synchronization is established even if the
An FM multiplex broadcast receiver, wherein the means does not establish frame synchronization . 2. Block synchronization is lost within one frame
Continuity monitoring means for monitoring whether or not the block synchronization is deviated within one frame.
2. The FM of claim 1 , wherein the vertical error correction is not performed.
Multiplex receiver. 3. A frame reproduction detection by detecting a BIC change point.
The frame synchronization establishing means and the frame synchronization reproduction.
The frame synchronization confirmation operation performed by each of the means
The frame synchronization depends on the result of the earlier synchronization.
Establishing the claim 1 or 2 FM multiplex broadcasting receiver according. 4. The method according to claim 1, wherein the horizontal blocks of the cyclic code are interleaved.
Receive the data with the product code frame
In an FM multiplex broadcasting receiver, a certain horizontal block is regarded as a temporary head block of a frame.
Vertical direction error revised against was the solution None interleaved data
A vertical error correction means for performing correction, a frame reset by using the vertical error correction result.
Detecting the synchronous front protection means and the BIC change point
A frame synchronous reproduction unit for performing frame synchronous reproduction, wherein the frame synchronous forward protection unit includes the frame synchronous reproduction unit;
Not only reset by means, but also
Note that resetting is performed using the result of error correction
And symptoms, FM multiplex broadcasting receiver.