JP2663866B2 - Packet majority circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is suitable for use in packet transmission for transmitting a data signal using a data channel such as a television satellite broadcast.

[0002]

2. Description of the Related Art In pay broadcasting in satellite broadcasting, it is essential to scramble video and audio, so a scramble decoder (hereinafter, referred to as "scrambling decoder") for canceling the scrambling is required.
Decoder). In this decoder, in order to descramble the scrambled video and audio, it is necessary to transmit a descrambling encryption key to the receiving side. For this reason, a method of transmitting common information and individual information including an encryption key using an empty voice channel is generally used. Then, a random signal is generated by a pseudo-random signal generator using the encryption key, and the scrambled video and audio are restored to the original video and audio.

The encryption key is appropriately changed depending on time in order to increase the difficulty of restoration due to unauthorized viewing and to secure more security. Therefore, a packet transmission method that is confidential and resistant to errors is very important in pay broadcasting.

[0004] Since common information is particularly important, five consecutive transmissions are performed.
The signal processing flow is such that a packet majority decision is made using the first three packets among them, error correction is performed, and SDSC correction that can correct an error of 8 bits or less is performed. And in broadcasting it has already been put to practical use, when the normally can receive a packet of five common information, the last fourth and the fifth packet without packet number <br/> determined, the bit stream Karade - A method is used in which packet extraction data obtained by interleaving is output as it is.

As a prior art of such a packet majority circuit, there is a data transmission system described in Japanese Patent Application Laid-Open No. 62-131636, a block diagram of which is shown in FIG. This system ensures that data can be transmitted even at the time of C / N, which is close to the service limit, compared to sending only one packet.

[0006] Here, as a code having an extremely high error correction capability used as an error correction code for teletext, B
EST (Burst and random Error correction System f
or Teletext) code, but in the present invention, this BEST
The code is SDSC (Shorteneddifference Set Cyclic cod
e) Call it the sign. This SDSC code SDSC
FIG. 9 shows an example of the decoding circuit of (273, 191). The received signal is divided by a generator polynomial, and the complex parity check conversion circuit 23 converts the 82-bit syndrome of the register value in the division circuit 22 into a 17-bit composite parity.

Here, the number of the 17 bits that have become "1" is determined by the majority logic decision value setting unit 25 for error correction.
If the received data is equal to or larger than the set value, it is determined that there is an error in the received data, and the received signal is corrected by the exclusive OR 27 for each bit.

An advantage of the SDSC code is that the BCSC
That the decoding circuit can be configured much more easily than the H code, and that the error correction majority logic decision value setting unit 2
By repeating the correction operation while changing the set value of 5, the error correction capability can be further enhanced.

[0009]

However, when the majority decision of the packet of the common information is performed by the majority decision method, the bit error rate is increased, and the packet which is continuously transmitted by the header identification unit is removed. S
A problem that the SDSC error is not repeated a plurality of times the error correction operation by DSC correction unit, 5 for performing packet majority by 3 packets during continuous feeding, a problem that does not go majority by five packets all data was there.

An object of the present invention is to solve the above-mentioned problems, and an object of the present invention is to provide a packet majority circuit with high reliability and improved error correction.

[0011]

According to the present invention, a packet voting circuit according to the present invention newly includes a decision value setting section for header identification and an SDSC.
Even when the C / N close to the service limits by providing the error correction majority decision value setting unit for use, to as much as possible improves the recognition rate for packets want to packet number <br/> determined, the header identification unit To solve the problem that the packets that are sent multiple times are removed, and if the count value of the number of detected packets is less than a certain set value
The error correction operation is repeated a plurality of times by increasing the value of the majority decision value for error correction , and if the count value of the number of detected packets is larger than a certain set value, the value of the majority decision value is decreased (actually, the majority decision value is reduced). By fixing the value to 9 and performing error correction by the SDSC only once), the number of packets that cause an SDSC error is reduced.

Furthermore 5 of continuous feeding to the incoming common information packets, when to receive the 5 packets all the common information, output packet data path by a time three packets
The packet subjected to packet majority processing utilized again in the packet number <br/> determined process, eventually by performing majority decision by 5 packets, resistant to very bursty errors,
This is a means for solving the above-mentioned problem by providing a highly reliable satellite broadcast communication system.

[0013]

According to the packet voting circuit of the present invention, even when the C / N is close to the service limit, the recognition rate of a packet to be subjected to a packet voting is minimized by changing the determination value setting section for header identification with time. This has the effect of preventing the packets that have been sent multiple times in the header identification unit from being removed.

[0014] In addition, for a packet to be subjected to a majority decision, a majority decision value for error correction is set in accordance with the count value of the number of detected packets. in the majority decision value a value by increasing Repetitive a multiple error correcting operation <br/> Rikae Succoth, also is greater than the set value is the count value, by reducing the value of the majority decision value ,
The number of packets that cause an SDSC error can be reduced . SDS
Because it can set an optimum error correction majority logic decision value definitive in C decoding reduces the number of iterations of the error correction operation, S
This has the effect of increasing the speed of the DSC decoding circuit.

Here, the count value of the number of packets and the error
This is the relationship with the majority decision value for correction.
The count value is 1 despite the packets that should be
In the case of the chair 2, a considerable amount of noise was mixed during transmission.
And increase the majority decision value for error correction.
It is. Conversely, if the count value of packets
Sometimes it is judged that the transmission condition is good,
This is to reduce the regular majority decision value.

When the common information of all five of the five consecutively transmitted common information packets has been received, the packet majority processing of the first packet, the second packet, and the third packet is performed. By using the received packet again in the majority processing, a 5-bit packet majority circuit can be equivalently configured in spite of the 3-bit majority circuit, and all of the five packets received as a result can be used in the packet majority processing. This has the effect that a highly reliable packet majority circuit with improved error correction capability can be provided.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail based on embodiments. In the first embodiment, a packet majority circuit that increases the determination value of the header identification unit during reception of the multiple transmission packets is described in the first embodiment.
According to the count value of the number of detected packets, the
The packet majority circuit that sets the error correction majority logic decision value in Example 2, first, performs a packet majority by first and second and third packet data, the path
Describing the packet majority circuit that performs packet majority by the packet data and the fourth and fifth packet after packet majority processing in Example 3.

(Embodiment 1) FIGS. 1, 4 and 5 are views for explaining a first embodiment. 1, the packet extraction unit 1 obtains a 288-bit packet from the bit stream, and the header identification unit 2 determines whether the broadcast is a pay broadcast. Here, if the broadcast is not a pay broadcast, the following processing is not performed, and the process of the packet identification unit 3 is performed only during the pay broadcast.

[0019] performs multi successive sending has been that information or whether the packet majority information or other information identified by the packet identification unit 3 performs packet majority processing by 3 packet when the packet majority information, otherwise If it is the information of, it is output as it is. Here, regarding the operation at the time of the common information for packet majority, when the first packet is received, first, it is written into the memory (A) 5 as a storage means, and when the next second packet is received, it is stored in the memory (B) 6. Write. Then, at the third receives a packet 3 bits of the packet majority circuit 7 performs packet majority of the previous memory A, 1 th written to B and the second packet data and third packet data.

The selector 8 reads out the packet data written in the memory (A) 5 or the memory (B) 6 without deciding the majority of the packets when only two or less of the five consecutively transmitted packets can be received. Sometimes needed. Further, a counting unit 9 for the number of detected packets
Counts the number of the five consecutively transmitted packets, and switches the selectors 16 and 17 according to the count value.

The timer section 10 measures a predetermined time. The timer section 10 latches the value of the count section 9 of the number of detected packets after the lapse of the designated time in the delay section 11, and the latched value is 2 or less. time, path a packet data written in the memory (a) 5 or the memory (B) 6 of the aforementioned
This is necessary to perform the operation of reading without determining the majority of the packets .

[0022] Although the translation performed SDSC correct packet after packet majority processing obtained as described above, wherein the newly formed header identification determination value setting unit 18, one packet for packet <br/> majority Upon reception, the value set in the header identification determination value setting unit 18 is increased during the time when the packet is transmitted, thereby preventing the number of received packets from being reduced due to excessive errors in the header part.

FIG. 4 shows the state of packet processing at this time.
This will be described with reference to FIG. First, FIG. 4 shows C / C
This shows a case where the N ratio is very good. That performs packet <br/> majority by 3 packet upon receiving the third packet, the packet received in the fourth and fifth outputs it.

Next, FIG. 5A shows the state of signal processing when three packets have been removed from the five consecutively transmitted packets by the header identification unit. At this time, since only two packets can be received, the packet majority processing is not performed.
The packet output specification is as shown in FIG. However, as shown on the right side of FIG. 5B, when the determination value of the header identification unit 2 is increased during the time required for five consecutive transmissions from the time when the first one of the five consecutively transmitted packets is received, In the conventional example, there is a newly receivable packet among the packets having a header error.

For example, if the header is 16 bits
If the output of the judgment value setting unit 18 for header identification is 3,
Header error even if there are three errors in the header
Does not result in a header error if there are four errors.
You. However, the output of the header identification judgment value setting unit 18 is set to 4
To avoid a header error,
A packet that can be received is created.

FIG. 5B shows an example in which two new packets can be received. Since it means that can receive a total of four packets when, although the case shown in FIG. 5 (a) was not performed packet majority, since in the case shown in FIG. 5 (b) perform a packet majority, the received packet Can be reduced.

As a result, even when the C / N is near the service limit, packets can be received. That is, C / N
That when very low bit error too many, and increasing the number of detection packet as much for an error at the SDSC correction unit does not perform the packet multi <br/> number determined processing, the packet majority processing Thus, the bit error before the processing of the SDSC correction unit is reduced as much as possible.

Embodiment 2 FIG. 2 is a block diagram of a second packet majority circuit.

FIG. 2 shows a majority logic decision value setting section 19 for error correction , and based on the count value of the number of detected packets, an error occurs when the count value is smaller than a predetermined value.
When the count value is larger than a predetermined set value , the majority logic decision value for error correction is decreased (the lower limit is 9 in the case of the SDSC (273, 191) code). Things.

FIG. 6 shows the state of the packet processing.
Figure 6 left of each bit by 3 packets of (a) Paquet
Despite was Tsu door majority, SDSC correction section 1
4 shows a case where an error occurs. In order to improve this, in the present embodiment, as shown in FIG.
If (N: number of error corrections), the majority logic decision value for error correction of the SDSC correction unit 14 is started from M + 2, and is sequentially changed to M + 1 and M each time error correction is completed.
This is to perform DSC correction. However, M is a minimum value that is equal to or more than の of the minimum distance between codes of the difference set cyclic code.

In this case, since the SDSC correction capability is improved, compared with the case where the SDSC correction is not repeated, the SDS
It is possible to reduce the number of packets that cause a C error.

When the number of received packets is small as described above, it is considered that there is a considerable bit error in the packets that can be received. Therefore, the SDSC decoding circuit changes the majority logic decision value for error correction while changing the value. By repeating the correcting operation, the correcting capability is increased to reduce the number of packets that cause an SDSC error.

(Embodiment 3) FIG. 3 is a block diagram of a third packet majority circuit.

FIG. 3 is a circuit diagram of the circuit of FIG.
0 and 21 are provided so that the packet after the packet voting process can be used again in the next packet voting.

[0035] Thus Example 1, Example 2 and (feasible all combinations 5 C3 = 10 to choose three out of five) that can perform different combinations of packets majority Besides, packet by all 5 packets It is also possible to make a majority decision.

That is, when the first packet is received, it is written into the memory (A) 5 first, and when the next second packet is received, it is written into the memory (B) 6. And 3
Th When a packet is received at 3-bit packet majority circuit 7, the previous memory (A) 5, 1 th written in the memory (B) 6 and a packet of the second packet data and third packet data Make a majority decision.

Next, when the fourth packet is received,
Since the first and second packet data are written in the memories (A) 5 and (B) 6, the first, second and fourth packet data are stored.
The third packet data makes it possible to perform a majority decision on packets . Other combinations can be realized by switching the selectors 20 and 21. However, it is assumed that reading and writing of the memories 5 and 6 can be performed asynchronously.

Further, the data after the majority processing is written in place of the second packet data written in the memory (B) 6 simultaneously with the packet majority processing based on the first, second, and third packet data. When the fourth packet is written in the memory (A) 5 and the fifth data is received, the data after the packet majority processing by the first, second and third packet data (the data in the memory (B) 6) Data), the fourth (data in the memory (A) 5) and the fifth packet data
It is possible to make a majority decision on packets . FIG. 7 shows the state of the packet processing at this time.

Up to the middle of the packet voting process in FIG.
Although it in the same manner as in the conventional example, since the third packet after packet packet majority doing packet again majority using once majority packets, has become very small bit error packets. That is, equivalently enables packet majority by 5 packet while the packet majority by 3 packet, extremely reliable improvement.

[0040] provides two packets majority circuit and packet majority circuit for 5 packet for 3 packets to configure by other methods equivalent packet majority circuit and which, according to the count value of the detected packets, packets There is a method of switching the output of the majority decision circuit,
According to the present invention, since the same function can be realized only by the packet majority circuit for three packets, the number of required memories can be reduced.

This method can be expected to have a particularly effective effect when used in a communication system that requires extremely high reliability while being one-way communication.

[0042]

According to the packet majority circuit of the present invention as described above, according to the present invention, even when by changing the header identification determination value setting unit time close C / N service limit, wants to packet majority packet Has an effect that the recognition rate can be improved as much as possible, so that the packet transmitted in multiple at the header identification unit is not removed.

[0043] Also or to have it packets majority, by setting the majority decision value for optimum SDSC according to the count value of the detected number of packets, when the following settings count value is the for error correction When the value of the majority decision value is increased and the error correction operation is repeated a plurality of times, and when the count value is larger than a certain set value, the value of the error correction majority decision value is decreased to reduce the number of packets that cause an SDSC error. This has the effect that the time required for the SDSC decoding circuit can be minimized in accordance with the received packet status.

When the common information of all five of the five consecutively transmitted common information packets has been received, the packet majority processing of the first packet, the second packet, and the third packet is performed. By using the received packet again for the next packet voting process, a 5-bit packet voting circuit can be equivalently configured while using a 3-bit packet voting circuit, and all of the five received packets can be used for the packet voting process. Since it can be used, there is an effect that a highly reliable packet majority circuit with improved error correction capability can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram of a packet majority circuit according to a first embodiment of the present invention;

FIG. 2 is a block diagram of a packet majority circuit according to a second embodiment of the present invention;

FIG. 3 is a block diagram of a packet majority circuit according to a third embodiment of the present invention;

FIG. 4 is a diagram showing a normal packet majority decision processing method;

5A is a diagram showing a conventional packet output method. FIG. 5B is a diagram showing a packet majority processing method in the first embodiment of the present invention.

6A is a diagram showing a conventional packet output method. FIG. 6B is a diagram showing a packet majority processing method in the second embodiment of the present invention.

FIG. 7 is a diagram showing a packet majority processing method according to a third embodiment of the present invention;

FIG. 8 is a block diagram of a packet majority circuit according to the related art.

FIG. 9 is a block diagram of an SDSC code decoding circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Packet extraction part 2 Header identification part 3 Packet identification part 5, 6 272-bit memory 7 3-bit packet majority circuit 9 Receiving packet number counting part 10 Timer part 13 Memory write / read address generation circuit 14 SDSC correction part 15 packet identification unit 16, 17 selector 18 header identification judgment value setting unit 19 error correction majority decision logical judgment value setting unit 20, 21 selector

Claims (3)

(57) [Claims] 1. A packet extracting unit for extracting a packet multiplexed on a data channel, identifying whether or not the packet obtained by the packet extracting unit is a packet related to a pay broadcast, and receiving a packet from a header identification determination value setting unit. Setting
Bits that differ from the predetermined header code up to the number of values
A header identification unit that determines that the packet is a header even if the number of packets exists, a first packet identification unit that identifies the type of pay broadcast packet obtained by the header identification unit , Storage means for holding the first data and the second data in the case of a packet which has been transmitted in multiple transmissions based on the output of the packet discriminating unit, and a majority decision for each bit of the three packets can be performed. a majority circuit for bit, and the packet count unit for counting the number of packets of the packet being multi continuous feeding, and a timer unit to measure a time from reception of the first packet of the packets being multi continuous transmission , a flip-flop for latching the count value of the packet counting unit by the pulse from the timer part, SD to perform error correction of the packet after the packet majority processing A C-correction unit, and a second packet identification unit for re-identifying the type of the packet error-corrected by the SDSC correction unit, wherein the header identification unit is used for a designated time based on an output signal from the timer unit. A packet majority circuit, wherein a value of a judgment value setting unit is increased. 2. In a pay satellite broadcasting packet transmission system, when a count value of a detected packet number counting section is smaller than a predetermined value, a majority logic decision value for an SDSC correction section is set by a majority logic decision value setting section. 2. The packet majority circuit according to claim 1, wherein the packet majority is increased. 3. In a pay satellite broadcast packet transmission system, a packet is transmitted once in a first packet, a second packet, and a third packet out of five consecutively transmitted packets.
Performed DOO majority, then again path at the post packet majority processing packet and fourth packet and the fifth packet
2. The packet majority circuit according to claim 1, wherein a majority decision is made.