JPS613529A - Error correction system - Google Patents

Abstract

PURPOSE:To simplify a transmitter/receiver for a convolutionally coded signal by applying convolution coding after a synchronizing signal is incorporated into a digital signal to be transmitted. CONSTITUTION:In a transmission system transmitting a prescribed periodic signal, a synchronizing word 4 is inserted and incorporated to a digital signal 1 to be transmitted via a synchronous word (signal) insertion circuit 6, convolution coding for error correction is executed and transmitted by a coder 5, and after a reception side decodes a coded digital signal, the digital signal is detected separately. Thus, it is not required to provide two systems of clock circuits and a decoding circuit in follow-up to a clock faster than the transmission speed of data and simple circuit constitution is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a maximum likelihood decoding method in a transmission system having a synchronous code with a constant period.

[Prior art and problems]

Conventionally, this type of system has adopted a configuration in which only the transmitted digital signal is first subjected to convolutional encoding, and then a synchronization word is added.

FIG. 1 is a block diagram showing an example of the configuration of a conventional transmitting circuit, in which 1 is a transmitted smooth digital signal, 2 is a convolutionally encoded digital signal, and 3 is a transmitted digital signal with a synchronization word added. , 4 represents a synchronization word signal, 5 represents an encoding circuit, and 6 represents a synchronization word insertion circuit.

Figure 2 is a diagram showing examples of signals in each part of the transmitting circuit, and shows (1) to
(3) corresponds to 1 to 3 in Figure 1, respectively, and D1
~D4 represents data before encoding, C11~C24 represents data after encoding, and the shaded portion represents a synchronization word.

FIG. 3 is a block diagram showing an example of the configuration of a decoding circuit, in which 7 is a received demodulated signal, 8 is a synchronizing word separation circuit, 9 is a received demodulated signal from which the synchronizing word has been separated, 10 is a decoding circuit, 11 represents the decoded transmitted B digital signal.

FIG. 4 is a diagram showing an example of signals in each part of the decoding circuit, (7),
(9) and (11) respectively correspond to 7.9°11 in Fig. 13, where 7 is the received demodulated signal, 9 is the received demodulated signal from which the synchronization word has been separated, and 11 is the decoded digital signal to be transmitted. The entire figure is shown, and D1 to D4, CI1 to C24, and hatched areas are the same as in FIG. 2.

The decoding circuit shown in FIGS. 1 and 3 is configured to remove the synchronization word from the received demodulated signal and perform Viterbi decoding on the received demodulated signal again as a continuous encoded signal.

In the conventional system using a combination of a transmitting circuit and a decoding circuit as described above, a synthesis circuit is required on the transmitting side to insert a synchronization word after encoding, and a synchronization word section is required on the receiving side for decoding. This requires a function to stop the circuit operation, which complicates the circuit configuration and control, and the transmission characteristics are the same as when only encoded signals are sent and received, excluding the synchronization word, and the information of the synchronization word is The drawback was that it did not contribute to error correction.

FIG. 5 is a block diagram showing another example of the configuration of a conventional decoding circuit, in which 7 is a received demodulated signal, 12 is a synchronization word separation "θ
``insertion circuit, 13 is a clock switching circuit, 10 is a decoding circuit, 11 is a cram school digital signal to be transmitted, 14 is a high-speed clock, 14' is a clock having the same speed as the transmission speed, 15 is an input signal of the decoding circuit, 16 represents a clock signal.

Figure IIpi6 is a diagram showing examples of signals in each part of the decoder circuit, where (7), (15), (16), and (11) correspond to 7.15.16.11 in Figure 5, respectively. 7
15 is the received demodulated signal, 15 is the decoding circuit input signal excluding the synchronization word and inserting "θ", 16 is the ack signal, 11 is the decoded digital signal to be transmitted, 4 is the synchronization word, and 17 is "
It represents the θ″ signal.

In this example, the synchronization word is removed from the received demodulated signal,
A configuration is adopted in which '0''' is inserted and the decoding circuit is reset.

In this conventional method, in order to reset the decoding circuit, it is necessary to complete the reset using a clock faster than the transmission speed while the synchronization word is being received, so two systems of clock circuits and the corresponding clock are used. The disadvantage is that the circuit configuration is complicated and control is difficult, such as requiring a clock switching circuit and a decoding circuit that can follow a fast clock.

[Purpose of the invention]

In order to solve the above-mentioned conventional drawbacks, the present invention performs communication using a digital signal in which a digital signal to be transmitted and a synchronization word are simultaneously encoded. The purpose of the present invention is to provide a Wkg correction method that has high signal efficiency (also, does not require signal processing faster than the clock speed and can be implemented with a simple circuit).

Hereinafter, the configuration and the like will be explained in detail based on the drawings of the embodiments.

〔Example〕

Hereinafter, regarding the description of the embodiments of the present invention, please refer to l! In order to explain the process concisely, we will describe the case where the encoding is set to have a transmission efficiency of 1/2, a constraint length of 3, polynomials i+xx", ixx", and a synchronization sit of 3.

FIG. 7 is a block diagram showing the configuration of a transmitting circuit according to an embodiment of the present invention, in which 1 represents a digital signal to be transmitted, 6
5 represents a synchronization word insertion circuit, 5 represents an encoding circuit, and 19 represents an encoded transmission digital signal.

Figure 8 is a diagram showing the signals of each part of the transmitting circuit, (1), (1
8) and (19) correspond to 1.18.19 in Fig. 7, where 1 represents the digital signal to be transmitted, 18 represents the signal with a synchronization word inserted, and 19 represents the encoded transmission digital signal. . *In addition, 20 indicates an encoded signal generated from a digital signal adjacent to the synchronization word, and 21 indicates a fixed pattern determined by the synchronization word.

FIG. 9 is a block diagram showing a decoding circuit according to an embodiment of the present invention, in which 22 is a metric calculation circuit, 23 is a path memory, 24 is a path memory selection circuit, 18 is an input signal, 25
26 represents a maximum likelihood determination circuit, and 27 represents a signal that forcibly selects a path.

This circuit performs normal Viterbi decoding where there is no synchronization word, and performs metric calculation using the known fixed pattern instead of the received signal only when it receives the fixed pattern 21 that is decoded in 7 frame periods. In addition, in the maximum likelihood path judgment, 25
It operates as if it were to make a determination according to the synchronization word pattern detected by the method.

Figure 10 is a diagram showing the transition of the state of the decoding circuit after selecting an incorrect path. 28 is the characteristic of the conventional decoding method using all "θ" inputs and a reset type, and 29 is the characteristic of the conventional synchronous word input decoding method. 30 is a characteristic of the decoding method of the present invention, 31 is a correct transition, and 32 is a synchronization word length.

As is clear from the figure, compared to the conventional decoding method that removes synchronization words, the time to return to the correct path is faster and the error correction ability is greater.

(Effects of the Invention) As described above in detail, according to the method of the present invention,
There is an advantage that the device can be realized with a simple circuit configuration without requiring two systems of clock circuits or a decoding circuit that follows a clock faster than the data transmission speed.

Furthermore, since the synchronization word information can be made to contribute to error correction, communication with high decoding efficiency can be realized, which is highly effective.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the configuration of a conventional transmitting circuit, FIG. 2 is a diagram showing an example of signals in each part of the transmitting circuit, and FIG. 3 is a block diagram showing an example of the configuration of a decoding circuit. Fig. 4 is a diagram showing an example of signals in each part of the decoding circuit, Fig. 5 is a block diagram showing another example of the configuration of a conventional decoding circuit, and Fig. 6 is a diagram showing an example of signals in each part of the decoding circuit. 7 is a block diagram showing the configuration of a transmitting circuit according to an embodiment of the present invention, FIG. 8 is a diagram showing signals of each part of the transmitting circuit, and FIG. 9 is a block diagram showing the configuration of a transmitting circuit according to an embodiment of the present invention. The block diagram shown in FIG. 10 is J! of the state of the decoder circuit after selecting the wrong path. FIG. 1...Digital signal to be transmitted, 2...
...Convolutionally encoded digital signal, 3...
...Transmission digital signal with synchronization word added, 4...
... Synchronization word signal, 5 ... Encoding circuit, 6 ...
... Synchronization word insertion circuit, 7 ... Received demodulated signal, 8 ... Synchronization W! Separation circuit, 9... Received demodulated signal from which the synchronization word has been separated, 10... Decoding circuit, 11... Decoded digital signal to be transmitted, 12... ... Synchronous word separation "θ" insertion circuit, 13
...... Clock switching circuit, 14... High speed clock, 14'... Clock at the same speed as the transmission speed, 15... Input signal of decoder circuit, 16・
... Clock signal, 17 ... "θ" signal 18 ... Signal with synchronization word inserted, 19 ...
...Encoded transmission digital signal, 20...Encoded signal generated from the digital signal adjacent to the synchronization word, 21...Fixed pattern determined by the synchronization word, 22... ...Metric calculation circuit, 23...
...Path memory, 24...Path memory selection circuit %25...Signal for forcibly inputting a fixed pattern, 26...Maximum likelihood determination circuit, 27. ...
...Signal for forcibly selecting a path, 28...Characteristics of the conventional reset type that inputs all "θ", 29.
...Characteristics of the conventional multicoding method for decoding excluding synchronization words, 30...Characteristics of the multicoding method of the present invention, 31...
...Correct transition, 32...Synchronized LLI Chief Agent Patent Attorney Book 1111 Takashi
/ times Figure 2 Figure 3 Figure 4 Figure 6 Figure 6 (If) n "] []] Figure 7 Figure 5 zO/lt/

Claims (1)

[Claims] (1) In a transmission system that transmits a signal that synchronizes at a constant cycle, a digital signal to be transmitted on the transmitting side and a digital signal that integrates a synchronization word are convolutionally encoded to produce an encoded digital signal. An error correction method characterized in that the encoded digital signal is transmitted as an encoded digital signal, and after decoding the encoded digital signal on the receiving side, the digital signal to be transmitted is separated and detected. (2) A part of the received signal is replaced with a specific bit at each frame timing by establishing synchronization before or after decoding on the receiving side and using a detected or estimated synchronization word. Error correction method. (3) The error correction method according to claim (1) or (2), wherein the receiving side performs metric calculation of the maximum likelihood decoding circuit and selection of the maximum likelihood path according to the synchronization word.