JPH0152937B2 - - Google Patents
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- Publication number
- JPH0152937B2 JPH0152937B2 JP59123652A JP12365284A JPH0152937B2 JP H0152937 B2 JPH0152937 B2 JP H0152937B2 JP 59123652 A JP59123652 A JP 59123652A JP 12365284 A JP12365284 A JP 12365284A JP H0152937 B2 JPH0152937 B2 JP H0152937B2
- Authority
- JP
- Japan
- Prior art keywords
- digital signal
- decoding
- synchronization word
- signal
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000005540 biological transmission Effects 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 11
- 238000007476 Maximum Likelihood Methods 0.000 claims description 6
- 238000012937 correction Methods 0.000 claims description 6
- 238000004364 calculation method Methods 0.000 claims description 5
- 238000001514 detection method Methods 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 21
- 238000003780 insertion Methods 0.000 description 5
- 230000037431 insertion Effects 0.000 description 5
- 238000000926 separation method Methods 0.000 description 4
- 230000007704 transition Effects 0.000 description 4
- 238000004891 communication Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
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- Error Detection And Correction (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は一定周期の同期符号を有する伝送系に
おける最尤復号方式に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a maximum likelihood decoding method in a transmission system having a synchronous code with a constant period.
従来、この種の方式においては先に送信デイジ
タル信号のみについて、たたみ込み符号化を行な
い、その後、同期語を付加する構成が採られてい
た。
Conventionally, this type of system has adopted a configuration in which only the transmitted digital signal is first subjected to convolutional encoding, and then a synchronization word is added.
第１図は従来の送信回路の構成の１例を示すブ
ロツク図であつて、１は伝送すべきデイジタル信
号、２はたたみ込み符号化されたデイジタル信
号、３は同期語を付加した送信デイジタル信号、
４は同期語信号、５は符号化回路、６は同期語挿
入回路を表わしている。 FIG. 1 is a block diagram showing an example of the configuration of a conventional transmitting circuit, in which 1 is a digital signal to be transmitted, 2 is a convolutionally encoded digital signal, and 3 is a transmitted digital signal with a synchronization word added. ,
4 represents a synchronization word signal, 5 an encoding circuit, and 6 a synchronization word insertion circuit.
第２図は送信回路各部の信号の例を示す図で、
１〜３はそれぞれ第１図の１〜３に対応してお
り、Ｄ１〜Ｄ４は符号化前のデータ、Ｃ１１〜Ｃ
２４は符号化後のデータ、斜線を施した部分は同
期語を示している。 Figure 2 is a diagram showing an example of signals in each part of the transmitting circuit.
1 to 3 correspond to 1 to 3 in FIG. 1, respectively, D1 to D4 are data before encoding, and C11 to C
Reference numeral 24 indicates encoded data, and the shaded portion indicates a synchronization word.
第３図は復号回路の構成の１例を示すブロツク
図であつて、７は受信復調信号、８は同期語分離
回路、９は同期語を分離した受信復調信号、１０
は復号回路、１１は復号した伝送すべきデイジタ
ル信号を表わしている。 FIG. 3 is a block diagram showing an example of the configuration of a decoding circuit, in which 7 is a received demodulated signal, 8 is a synchronization word separation circuit, 9 is a received demodulated signal from which a synchronization word has been separated, and 10
11 represents a decoding circuit, and 11 represents a decoded digital signal to be transmitted.
第４図は復号回路各部の信号の例を示す図で、
７，９，１１はそれぞれ第３図の７，９，１１に
対応しており、７は受信復調信号、９は同期語を
分離した受信復調信号、１１は復号した伝送すべ
きデイジタル信号を表わしていて、Ｄ１〜Ｄ４、
Ｃ１１〜Ｃ２４および斜線を施した部分などは第
２図と同様である。 FIG. 4 is a diagram showing an example of signals in each part of the decoding circuit.
7, 9, and 11 correspond to 7, 9, and 11 in FIG. 3, respectively, where 7 represents the received demodulated signal, 9 represents the received demodulated signal from which the synchronization word has been separated, and 11 represents the decoded digital signal to be transmitted. and D1 to D4,
C11 to C24 and the hatched portions are the same as in FIG. 2.
第３図の復号回路では、このように受信復調信
号から同期語を除き再び連続した符号化信号とし
て、ビタビ復号を行なう構成になつている。 The decoding circuit shown in FIG. 3 is configured to remove the synchronization word from the received demodulated signal and perform Viterbi decoding on the received demodulated signal again as a continuous encoded signal.
以上説明した送信回路と復号回路の組合わせに
よる従来の方式では、送信側では符号化した後同
期語を挿入するための合成回路が必要であり、受
信側では復号するために同期語部で回路動作を止
める機能が必要であつて、回路構成や制御が複雑
になるうえ、伝送特性は同期語を除き符号化信号
のみを送受した場合と同等になり、同期語の情報
を誤り訂正に寄与していないという欠点があつ
た。 In the conventional system using a combination of a transmitting circuit and a decoding circuit as described above, a synthesis circuit is required on the transmitting side to insert a synchronization word after encoding, and on the receiving side, a circuit is required in the synchronization word part for decoding. This requires a function to stop the operation, which complicates the circuit configuration and control, and the transmission characteristics are the same as when only encoded signals are sent and received, excluding the synchronization word, and the synchronization word information cannot be used to contribute to error correction. The drawback was that it was not.
第５図は従来の復号回路の構成の他の例を示す
ブロツク図であつて、７は受信復調信号、１２は
同期語分離“０”挿入回路、１３はクロツク切替
回路、１０は復号回路、１１は伝送すべきデイジ
タル信号、１４は高速クロツク、１４′は伝送速
度と同じ速度のクロツク、１５は復号回路の入力
信号、１６はクロツク信号を表わしている。 FIG. 5 is a block diagram showing another example of the configuration of a conventional decoding circuit, in which 7 is a received demodulated signal, 12 is a synchronization word separation "0" insertion circuit, 13 is a clock switching circuit, 10 is a decoding circuit, 11 is a digital signal to be transmitted, 14 is a high speed clock, 14' is a clock having the same speed as the transmission speed, 15 is an input signal to the decoding circuit, and 16 is a clock signal.
第６図は復号回路の各部の信号の例を示す図で
あつて、７，１５，１６，１１はそれぞれ第５図
の７，１５，１６，１１に対応しており、７は受
信復調信号、１５は同期語を除き“０”を挿入し
た復号回路入力信号、１６はクロツク信号、１１
は復号した伝送すべきデイジタル信号、４は同期
語、１７は“０”信号を表わしている。 FIG. 6 is a diagram showing an example of signals in each part of the decoding circuit, where 7, 15, 16, and 11 correspond to 7, 15, 16, and 11 in FIG. 5, respectively, and 7 is a received demodulated signal. , 15 is a decoding circuit input signal with "0" inserted except for the synchronization word, 16 is a clock signal, 11
4 represents a decoded digital signal to be transmitted, 4 represents a synchronization word, and 17 represents a "0" signal.
この例においては、受信復調信号から同期語を
除き、“０”を挿入し、復号回路をリセツトする
構成を採つている。 In this example, a configuration is adopted in which the synchronization word is removed from the received demodulated signal, "0" is inserted, and the decoding circuit is reset.
従来の、この方式においては、復号回路をリセ
ツトするため、同期語を受信している間に、伝送
速度より速いクロツクを用いてリセツトを完了し
なければならないから、２系統のクロツク回路と
該クロツクを切り替える回路および速いクロツク
に追従することのできる復号回路を必要とする
等、回路構成が複雑で制御が困難であるという欠
点があつた。 In this conventional method, in order to reset the decoding circuit, it is necessary to complete the reset using a clock faster than the transmission speed while the synchronization word is being received, so two systems of clock circuits and the clock are used. The disadvantage is that the circuit configuration is complicated and control is difficult, as it requires a circuit for switching the clock and a decoding circuit that can follow a fast clock.
本発明は上記従来の欠点を解決するため、伝送
すべきデイジタル信号と同期語を同時に符号化し
たデイジタル信号を用いて通信を行なうものであ
つて、同期語を有効に利用することが可能で復号
の効率が高く、また、クロツク速度より速い信号
処理をする必要がなく簡潔な回路で実現可能な誤
り訂正方式を提供することを目的としている。
In order to solve the above conventional drawbacks, the present invention performs communication using a digital signal in which a digital signal to be transmitted and a synchronization word are encoded at the same time, and the synchronization word can be effectively used and decoded. The purpose of the present invention is to provide an error correction method that has high efficiency, does not require signal processing faster than the clock speed, and can be implemented with a simple circuit.
以下、その構成等に関し実施例の図面に基づい
て詳細に説明する。 Hereinafter, the configuration and the like will be explained in detail based on the drawings of the embodiments.
以降、本発明の実施例の記述に関しては要点を
簡潔に説明するため符号化を伝送能率１／２、拘
束長３、多項式１＋Ｘ＋X2、１×X2とし、同期
語長が３の場合について述べる。
Hereinafter, regarding the description of the embodiments of the present invention, in order to briefly explain the main points, we will describe the case where the encoding is set to have a transmission efficiency of 1/2, a constraint length of 3, a polynomial of 1+X+X 2 , 1×X 2 , and a synchronization word length of 3. .
第７図は本発明の１実施例の送信回路の構成を
示すブロツク図であつて、１は伝送すべきデイジ
タル信号、６は同期語挿入回路、５は符号化回
路、１９は符号化送信デイジタル信号を表わして
いる。 FIG. 7 is a block diagram showing the configuration of a transmitting circuit according to an embodiment of the present invention, in which 1 is a digital signal to be transmitted, 6 is a synchronization word insertion circuit, 5 is an encoding circuit, and 19 is an encoded transmitting digital signal. represents a signal.
第８図は送信回路各部の信号を示す図で、１，
１８，１９は第７図の１，１８，１９に対応して
おり、１は伝送すべきデイジタル信号、１８は同
期語を挿入した信号、１９は符号化送信デイジタ
ル信号を表わしている。また、２０は同期語と隣
接するデイジタル信号から生成される符号化信
号、２１は同期語により決定される固定パターン
を示している。 FIG. 8 is a diagram showing the signals of each part of the transmitting circuit.
18 and 19 correspond to 1, 18, and 19 in FIG. 7, where 1 represents a digital signal to be transmitted, 18 represents a signal with a synchronization word inserted, and 19 represents an encoded transmission digital signal. Further, 20 indicates an encoded signal generated from a digital signal adjacent to the synchronization word, and 21 indicates a fixed pattern determined by the synchronization word.
第９図は本発明の１実施例の復号回路を示すブ
ロツク図であつて、２２はメトリツク演算回路、
２３はパスメモリ、２４はパスメモリ選択回路、
１８は入力信号、２５は固定パターンを強制的に
入力する信号、２６は最尤判定回路、２７は強制
的にパスを選択する信号を表わしている。 FIG. 9 is a block diagram showing a decoding circuit according to an embodiment of the present invention, in which 22 is a metric calculation circuit;
23 is a path memory, 24 is a path memory selection circuit,
Reference numeral 18 represents an input signal, 25 represents a signal for forcibly inputting a fixed pattern, 26 represents a maximum likelihood determination circuit, and 27 represents a signal for forcibly selecting a path.
この回路は同期語のない所では通常のビタビ復
号を行ない、フレーム周期に入力される固定パタ
ーン２１を受信した時のみ、受信信号ではなく既
知である固定パターンを用いてメトリツク演算を
行ない、また、最尤パス判定において、メトリツ
ク演算による結果ではなく、２５により検出した
同期語のパターンに従つて判定を行なうごとく動
作するものである。 This circuit performs normal Viterbi decoding where there is no synchronization word, and performs metric calculations using the known fixed pattern instead of the received signal only when it receives the fixed pattern 21 that is input in the frame period. In the maximum likelihood path determination, the determination is made according to the synchronization word pattern detected by 25, rather than the result of metric calculation.
第１０図は誤つたパスを選択した後の復号回路
の状態の変遷を示す図で、２８は従来のオール
“０”を入力するリセツト形の復号法の特性、２
９は従来の同期語を除いて復号する復号法の特
性、３０は本発明の復号法の特性、３１は正しい
遷移を示しており、また、３２は同期語長を示し
ている。 FIG. 10 is a diagram showing the transition of the state of the decoding circuit after selecting an incorrect path. 28 is the characteristic of the conventional reset-type decoding method that inputs all "0";
Reference numeral 9 indicates the characteristic of the conventional decoding method for decoding excluding the synchronization word, 30 indicates the characteristic of the decoding method of the present invention, 31 indicates a correct transition, and 32 indicates the synchronization word length.
図より明らかなように、従来の同期語を除去す
る復号法に比べて、正しいパスに戻る時間が速
く、誤り訂正能力の大きいことがわかる。 As is clear from the figure, compared to the conventional decoding method that removes synchronization words, the time to return to the correct path is faster and the error correction ability is greater.
以上、詳細に説明したように、本発明の方式に
よれば、クロツク回路を２系統設けたり、データ
の伝送速度より速いクロツクに追従する復号回路
などを必要とすることなく、簡潔な回路構成で装
置を実現することができる利点がある。また、同
期語情報を誤り訂正に寄与せしめることができる
ので復号効率の高い通信を実現し得るから効果は
大である。
As explained above in detail, the method of the present invention does not require two systems of clock circuits or a decoding circuit that follows a clock faster than the data transmission speed, and can be configured with a simple circuit configuration. There is an advantage that the device can be realized. Furthermore, since the synchronization word information can be made to contribute to error correction, communication with high decoding efficiency can be realized, which is highly effective.
第１図は従来の送信回路の構成の１例を示すブ
ロツク図、第２図は送信回路各部の信号の例を示
す図、第３図は復号回路の構成の１例を示すブロ
ツク図、第４図は復号回路各部の信号の例を示す
図、第５図は従来の復号回路の構成の他の例を示
すブロツク図、第６図は復号回路各部の信号の例
を示す図、第７図は本発明の１実施例の送信回路
の構成を示すブロツク図、第８図は送信回路各部
の信号を示す図、第９図は本発明の１実施例の復
号回路を示すブロツク図、第１０図は誤つたパス
を選択した後の復号回路の状態の変遷を示す図で
ある。
１……伝送すべきデイジタル信号、２……たた
み込み符号化されたデイジタル信号、３……同期
語を付加した送信デイジタル信号、４……同期語
信号、５……符号化回路、６……同期語挿入回
路、７……受信復調信号、８……同期語分離回
路、９……同期語を分離した受信復調信号、１０
……復号回路、１１……復号した伝送すべきデイ
ジタル信号、１２……同期語分離“０”挿入回
路、１３……クロツク切替回路、１４……高速ク
ロツク、１４′……伝送速度と同じ速度のクロツ
ク、１５……復号回路の入力信号、１６……クロ
ツク信号、１７……“０”信号、１８……同期語
を挿入した信号、１９……符号化送信デイジタル
信号、２０……同期語と隣接するデイジタル信号
から生成される符号化信号、２１……同期語によ
り決定される固定パターン、２２……メトリツク
演算回路、２３……パスメモリ、２４……パスメ
モリ選択回路、２５……固定パターンを強制的に
入力する信号、２６……最尤判定回路、２７……
強制的にパスを選択する信号、２８……従来のオ
ール“０”を入力するリセツト形の特性、２９…
…従来の同期語を除いて復号する復号法の特性、
３０……本発明の復号法の特性、３１……正しい
遷移、３２……同期語長。
FIG. 1 is a block diagram showing an example of the configuration of a conventional transmitting circuit, FIG. 2 is a diagram showing an example of signals in each part of the transmitting circuit, and FIG. 3 is a block diagram showing an example of the configuration of a decoding circuit. 4 is a diagram showing an example of signals in each part of the decoding circuit, FIG. 5 is a block diagram showing another example of the configuration of a conventional decoding circuit, FIG. 6 is a diagram showing an example of signals in each part of the decoding circuit, and FIG. 7 is a diagram showing an example of signals in each part of the decoding circuit. 8 is a block diagram showing the configuration of a transmitting circuit according to an embodiment of the present invention. FIG. 8 is a diagram showing signals of each part of the transmitting circuit. FIG. 9 is a block diagram showing a decoding circuit according to an embodiment of the present invention. FIG. 10 is a diagram showing the transition of the state of the decoding circuit after selecting an erroneous path. 1... Digital signal to be transmitted, 2... Convolutionally encoded digital signal, 3... Transmission digital signal with synchronization word added, 4... Synchronization word signal, 5... Encoding circuit, 6... Synchronization word insertion circuit, 7... Received demodulated signal, 8... Synchronization word separation circuit, 9... Received demodulated signal from which the synchronization word has been separated, 10
...Decoding circuit, 11...Decoded digital signal to be transmitted, 12...Synchronization word separation "0" insertion circuit, 13...Clock switching circuit, 14...High speed clock, 14'...Same speed as transmission speed clock, 15... input signal of decoding circuit, 16... clock signal, 17... "0" signal, 18... signal with synchronization word inserted, 19... coded transmission digital signal, 20... synchronization word and an encoded signal generated from an adjacent digital signal, 21...Fixed pattern determined by the synchronization word, 22...Metric calculation circuit, 23...Path memory, 24...Path memory selection circuit, 25...Fixed Signal for forcibly inputting a pattern, 26... Maximum likelihood judgment circuit, 27...
Signal for forcibly selecting a path, 28...Characteristics of the conventional reset type that inputs all "0"s, 29...
...Characteristics of the conventional decoding method that excludes synchronization words,
30...Characteristics of the decoding method of the present invention, 31...Correct transition, 32...Synchronization word length.
Claims (1)
において、送信側で伝送すべきデイジタル信号と
同期語を一体化したデイジタル信号をたたみ込み
符号化して符号化デイジタル信号として送信する
と共に、受信側で該符号化デイジタル信号を復号
した後、伝送すべきデイジタル信号を分離検出す
る復号検出方法において受信側で復号前または復
号後に同期を確立して検出または推定した同期語
によりフレームタイミングごとに受信信号の一部
を特定ビツトで置き換えることを特徴とする誤り
訂正方式。 ２ 一定周期で同期をとる信号を伝送する伝送系
において、送信側で伝送すべきデイジタル信号と
同期語を一体化したデイジタル信号をたたみ込み
符号化して符号化デイジタル信号として送信する
と共に、受信側で該符号化デイジタル信号を復号
した後、伝送すべきデイジタル信号を分離検出す
る復号検出方法において、受信側で最尤復号回路
のメトリツク演算及び最尤バスの選択を同期語に
従つて行なうことを特徴とする誤り訂正方式。[Claims] 1. In a transmission system that transmits signals that synchronize at a constant cycle, a digital signal to be transmitted on the transmitting side and a digital signal that integrates a synchronization word are convolutionally encoded and transmitted as an encoded digital signal. At the same time, in a decoding detection method that separates and detects the digital signal to be transmitted after decoding the coded digital signal on the receiving side, synchronization is established on the receiving side before or after decoding, and the detected or estimated synchronization word is used to detect the frame. An error correction method that replaces part of the received signal with specific bits at each timing. 2. In a transmission system that transmits a signal that synchronizes at a constant period, the transmitting side convolutionally encodes the digital signal to be transmitted and the digital signal that integrates the synchronization word and transmits it as a coded digital signal, and the receiving side In the decoding and detection method for separating and detecting the digital signal to be transmitted after decoding the encoded digital signal, the receiving side performs metric calculation of the maximum likelihood decoding circuit and selection of the maximum likelihood bus according to a synchronization word. An error correction method that uses
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12365284A JPS613529A (en) | 1984-06-18 | 1984-06-18 | Error correction system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12365284A JPS613529A (en) | 1984-06-18 | 1984-06-18 | Error correction system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS613529A JPS613529A (en) | 1986-01-09 |
| JPH0152937B2 true JPH0152937B2 (en) | 1989-11-10 |
Family
ID=14865909
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12365284A Granted JPS613529A (en) | 1984-06-18 | 1984-06-18 | Error correction system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS613529A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02112322A (en) * | 1988-10-21 | 1990-04-25 | Nec Corp | Error correction encoding method |
| JPH0555932A (en) * | 1991-08-23 | 1993-03-05 | Matsushita Electric Ind Co Ltd | Error correction coding and decoding device |
| US6118825A (en) * | 1997-08-11 | 2000-09-12 | Sony Corporation | Digital data transmission device and method, digital data demodulation device and method, and transmission medium |
| KR100593580B1 (en) * | 1997-08-11 | 2006-06-28 | 소니 가부시끼 가이샤 | Digital broadcast signal transmission apparatus and method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5374806A (en) * | 1976-12-15 | 1978-07-03 | Nec Corp | Error correction encoder |
-
1984
- 1984-06-18 JP JP12365284A patent/JPS613529A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5374806A (en) * | 1976-12-15 | 1978-07-03 | Nec Corp | Error correction encoder |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS613529A (en) | 1986-01-09 |
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