JPS5912653A - Synchronizing circuit of error correcting decoder - Google Patents

Abstract

PURPOSE:To attain the synchronism of a code word at an error correcting decoder itself, by using a discriminating signal of an error correcting signal as a phase shift amount control signal. CONSTITUTION:A decoding signal is outputted at a terminal 101 from a signal to be decoded inputted to a terminal 100 through a phase shifter 10 and an error correcting signal is outputted to a terminal 102. The error correcting signal is integrated for a prescribed time at an integrator 20 and then applied to a threshold value circuit 30, and the discriminating signal is outputted when the value is a prescribed value or below or over. Since the rate generating a negative signal is increased in the error correcting signal more than the case with the correct synchronism in receiving the signal to be decoded at the state of out of synchronism, the state of synchronism/asynchronism is discriminated by observing the discriminating signal. Thus, the synchronism is obtained by applying the discriminating signal to the phase shifter 10 as a phase shift amount control signal.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronization circuit for an error correction decoder.

In digital communications, it is well known that one method of reducing transmission errors is to transmit transmitted information after being error-corrected encoded, and to perform error-correction decoding on the received code.

For example, various encoded decoding methods are described in detail in the publication "Coding Theory" published by Shokodo Co., Ltd. in October 1973.

When performing error correction encoding, the transmission information bit string is encoded using a predetermined method and transmitted as codewords, so the receiving side extracts the codewords in synchronization with the encoding on the transmitting side and corrects errors. It must be input to the correction decoder. For this synchronization, conventionally a synchronization signal from an external system, e.g.
'CM frame synchronization signals were used. However, this conventional method has the disadvantage that the synchronization circuit must be designed for each system because the format of the synchronization signal differs from system to system. Furthermore, in systems where it is difficult to obtain a frame synchronization signal, it is difficult to design a synchronization circuit.

The present invention eliminates the drawbacks of the conventional method and provides a synchronization circuit that can synchronize code words in an error correction decoder itself.

According to the present invention, the phase shifter is configured as a synchronization circuit used for an error correction decoder having a decoded signal input terminal, an error correction signal output terminal, and a decoded signal output terminal, and has a phase shift amount control terminal. an integrator that receives the output from the error correction signal output terminal; a threshold circuit that outputs an identification signal when the output of the integrator is above or below a predetermined value; An error correction decoder characterized in that a phase shift amount control signal of a phase shifter, the decoded signal is used as an input signal of the phase shifter, and an output signal of the phase shifter is used as an input signal of the error correction decoder. A synchronous circuit is obtained.

Further, the circuit is configured as a synchronization circuit used for an error correction decoder having a decoded signal input terminal and a decoded signal output terminal, and includes a phase shifter having a phase shift amount control terminal, and a phase shifter having a phase shift amount control terminal, and a phase shifter having a phase shift amount control terminal. a buffer for storing time; an error correction encoding circuit for re-encoding the output of the error correction decoder; a correlator for correlating the output of the encoding circuit with the signal read from the buffer; and an output of the correlator. a threshold circuit that outputs an identification signal when the signal is above or below a predetermined value; the identification signal is used as a phase shift amount control signal for the phase shifter; A synchronization circuit for an error correction decoder is obtained, characterized in that the output signal of the phase shifter is used as an input signal to the error correction decoder and the buffer.

Next, the present invention, together with its principles, will be explained in detail with reference to the drawings.

Fig. 1 is a block diagram showing a first embodiment in which a synchronization circuit of the present invention is added to an error correction decoder, Figs. 2 to 4 are block diagrams showing an example of a phase shifter, and Fig. 5 is a block diagram showing an example of a phase shifter. FIG. 2 is a block diagram showing a second embodiment in which a synchronization circuit is added to an error correction decoder.

First, a first embodiment will be explained with reference to FIG.

In FIG. 1, the decoded signal input to the terminal 100 is
The signal is applied to the decoded signal input terminal 104 of the error correction decoder 200 through the phase shifter 10. A decoded signal is output to the terminal 10, and an error correction signal obtained by correcting the decoded signal in the error correction decoder 200 is output to the terminal 02. For example, if a signal that corrects an erroneous signal is a negative signal, and a signal that is not corrected is a positive signal (of course, the reverse is also possible), when a decoded signal with many errors is received, the terminal 102 It can be seen that the number of negative signals increases.

Note that the error correction signal can also be obtained by multiplying the decoded signal by the decoded signal.

This fact will be used when explaining the second invention.

The error correction signal is applied to an integrator 2 and integrated for a certain period of time. The integrator is then reset and begins integrating the next input signal. The integrated output of the integrator 20 is applied to a threshold circuit 30, which outputs an identification signal when the integrated output becomes less than or more than a predetermined value.

Now, when a signal to be decoded is received in an out-of-synchronization state, the error correction decoder decodes the signal as if it had received a signal in which errors were superimposed on the correct signal at most of the time points.

Therefore, the error correction signal has a higher proportion of negative signals than when synchronization is properly achieved.

Therefore, by observing the identification signal output from the threshold circuit 30, it is possible to determine whether the system is in a synchronous state or an asynchronous state at the time of observation. The identification signal is
A secret phase amount control signal for the phase shifter IO is supplied to terminal No. 103 of the phase shifter.

tx, the transmission code that can be error-corrected and encoded is sent to the transmitter by manually inputting the past multiple 11's for each information bit. Since the input signal I is output as an output signal and +S is generated, a signal (hereinafter referred to as a word synchronization signal) to indicate the division of this slope number of signals is applied to the terminal 105ζ. The synchronization signal is output to terminal 106 through phase shifter 10 and supplied to error correction decoder 200.

The phase shifter 10 is configured as shown in FIG. 2 or 3, for example. In FIG. 2, the decoded signal applied to terminal 100 is phase-shifted through phase-shifting element 120 and
The number is output. The word synchronization signal at terminal 105 is output as is to terminal 106 2, and the relative time relationship between the decoded signal and the word synchronization signal is adjusted.

In FIG. 3, the decoded signal applied to terminal 100 is output as is to terminal 104, and the word synchronization signal at terminal 105 is phase-shifted by phase shift element 130 and output to terminal 106. Note that the phase shift elements 120 and 130 are elements that include the following functions. That is,
This function is a counter that counts the number of times the identification signal arrives at the terminal 103, and a function that shifts the phase using a phase shifter determined in accordance with the counter output. In other words, it is an element that performs a function of shifting the phase by one each time an identification signal arrives.

Note that the maximum count number is, of course, the total number of phases that the decoded signal can take.

The above explanation has proceeded on the assumption that the signal to be decoded is a serial signal, but if the error correction decoder is designed to input parallel signals, for example, it is designed to input two parallel signals. In this case, as shown in FIG.
, 402 to switch 403.4.
By making the signals interchangeable with 04 and outputting them to terminals 406 and 407, phase shifts with equal constraints can be performed.

That is, the switching signal of the switch is applied to the terminal 405, and the input signal is set through the flip-flop 408 to a phase corresponding to the state of the flip-flop.

Next, a synchronization circuit of an error correction decoder according to a second aspect of the present invention will be explained.

Some error correction decoders do not provide an explicit error correction signal as shown in FIG.

For example, a decoder for non-linearly encoded non-systematic codes, a so-called Viterbi decoder, etc. are examples of such decoders.

The synchronization circuit for the error correction decoder according to the second aspect of the present invention uses only the decoded signal and the decoded signal for the error correction decoder, so it can be used even for a decoder that cannot obtain an error correction signal. It becomes.

It represents the same thing as 200, 101, 103-106.

Unlike the case in Figure 1, the synchronous circuit in Figure 5 distinguishes between synchronous and asynchronous states by receiving a signal obtained by re-encoding the decoded signal in the same manner as on the transmitting side. This is done by correlating with the decoded signal. In other words, if they are in a synchronous state, the correlation between both signals is extremely high, and if they are in an asymmetric 1υj state, the decoded signal is decoded as if an extremely large number of errors were superimposed on the transmitted signal. The degree of correlation between both A and No. 11 is extremely low. This allows us to distinguish between synchronous and asynchronous states.
f fil.

In FIG. 5, the buffer 50 is the error correction encoding circuit 40.
It has a fixed length for adjusting the temporal phase relationship between the re-encoded signal and the re-encoded signal. That is, the error correction decoder 200' and the error correction encoding circuit 4
1. Now, the output of the encoding circuit 40 and the output of the buffer 50 are input to the correlator 60, and the output of the correlator is input to the threshold circuit. 70. Then, the correlator output becomes less than or equal to a predetermined value.1. Outputs a poor identification signal.

The correlator 60 can be roughly divided into a multiplier 3v'I5 that takes the product of both the multiplier and the multiplier, and the integrator that agitates the output of the multiplier for a certain period of time, outputs it, and then resets it. Ru. Since the output of the multiplier is considered to correspond to the error correction signal as described above, the subsequent arrangement and operation are the same as in the case of FIG. Further, the fact that the present invention is effective even when the signal to be decoded is a parallel signal is explained in the fourth aspect as explained in connection with the first invention.
This can be explained using diagrams.

In addition, even if there is uncertainty in the carrier wave phase when the encoded signal is multiphase phase modulated and transmitted, the threshold value of the threshold circuit is appropriately determined, and the integration shown in Fig. 1 is performed. Uncertainty in the carrier wave phase can be removed by finding the carrier wave phase at which the output of the correlator becomes the largest, or the carrier wave phase at which the output of the correlator shown in FIG. 5 becomes the largest.

As described above in detail, the synchronization circuit of the error correction decoder according to the present invention enables word synchronization in the decoder itself without using a synchronization signal from an external system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of a synchronization circuit of the present invention and an error correction encoder to which the synchronization circuit is added, and FIGS. 2M to 4 are block diagrams showing examples of phase shifters. FIG. 5 is a block diagram showing a second embodiment of the synchronization circuit of the present invention and an error correction decoder to which the synchronization circuit is added. In the figure, to and to' are phase shifters, 200 and 200
' is the error correction decoder, 20 is the integrator, 30, 70
is a threshold circuit, 40 is an error correction coding circuit, and 6o is a threshold circuit.
is a correlator, 103 and 103' are phase shift amount control terminals, 105 and 105' are word synchronization signal input terminals, and terminal 1
04 and 104' are decoded signal output terminals after passing through the phase shifter, and terminals 105 and 105' indicate word synchronization signals after passing through the phase shifter, respectively. Figure 1 2. Figure 3 and =

Claims (2)

[Claims] (1) In a synchronization circuit used for an error correction decoder having a decoded signal input terminal, an error correction signal output terminal, and a decoded signal output terminal, a phase shifter having a phase shift amount control terminal; an integrator that receives the output from the error correction signal output terminal; a threshold circuit that outputs an identification signal when the output of the integrator is above or below a predetermined value; a phase shift amount control signal, the decoded signal is used as an input signal of the phase shifter, and the output signal of the phase shifter is used as an input signal of the error correction decoder. circuit. (2) In a synchronization circuit used for an error correction decoder having a decoded signal input terminal and a decoded signal output terminal, a phase shifter having a phase shift amount control terminal and a phase shifter having a phase shift amount control terminal, a buffer for storing time; an error correction encoding circuit for re-encoding the output of the error correction decoder; a correlator for correlating the output of the encoding circuit with the signal read from the buffer; a threshold circuit that outputs an identification signal when the output is above or below a predetermined value; the identification signal is used as a phase shift amount control signal for the phase shifter; A synchronization circuit for an error correction decoder, characterized in that an input signal and an output signal of the phase shifter are input signals to the error correction decoder and the buffer.