JPH0312505B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronization circuit for a Viterbi decoder.

In digital communications, one of the methods for reducing transmission errors is a Viterbi decoder. The principles and operation of the Viterbi decoder are described in Proceedings of the IEEE, No. 61, published by the IEEE in March 1973. Volume No. 3 No.
It is described in detail in the paper "The Viterbi Algorithm" listed on pages 268 to 218. In order to operate the Viterbi decoder, on the transmitting side, a transmission code is encoded in a predetermined method and transmitted as a code word. On the receiving side, code words are extracted in synchronization with the encoding on the sending side and input to the Viterbi decoder. For this synchronization, a conventional synchronization signal from an external system,
For example, PCM frame synchronization signals were used. However, this conventional method has the disadvantage that the synchronization circuit must be designed for each system because the formation of the synchronization signal differs from system to system. Furthermore, it has been difficult to apply the Viterbi decoder to systems where it is difficult to obtain a frame synchronization signal.

An object of the present invention is to eliminate the drawbacks of the conventional method and provide a synchronization circuit that can synchronize code words by observing the internal state of a Viterbi decoder. The configuration and operating principle of the present invention will be explained in detail below using the drawings.

FIG. 1 is a block diagram showing an embodiment of a Viterbi decoder to which a synchronization circuit according to the present invention is added. The decoded signal input to the terminal 100 is applied to the decoded signal input terminal 104 of the Viterbi decoder 200 through the phase shifter 10. A decoded signal is output to the terminal 101. The maximum metric determination circuit 20 in the synchronization circuit of the present invention includes a Viterbi decoder 2.
The metric of each branch selected by 00 and the state number having the metric are input to the register 30 as input signals. Then, the state number having the metric determined to be the maximum metric by the maximum metric determination circuit is set in the register 30.

The path determination circuit 40 determines whether a path exists between the state with the maximum metric at a past point in time and the state with the maximum metric at any other point in time, including the current time, and displays the determination result. The signal is applied to an integrator 50 and integrated. Note that the path determination circuit 40 can be configured using, for example, a read-only memory. The integral output of the integrator 50 is applied to a threshold circuit 50, which outputs an identification signal when the integral output becomes less than or equal to a predetermined value or more than a predetermined value. The identification signal is supplied to a terminal 103 of the phase shifter 10 as a phase shift amount control signal.

As shown in the example below, in the transmission code for Viterbi decoding, for each information bit that is sequentially input to the transmitter, multiple bits that depend on multiple past information bits are sequentially output as output bits. A synchronization signal (hereinafter simply referred to as a word synchronization signal) is applied to a terminal 105 to indicate the delimitation of the plurality of bits. The word synchronization signal is outputted to terminal 106 through phase shifter 10 and supplied to Viterbi decoder 200.

A portion 200 surrounded by a broken line in FIG. 1 shows the basic configuration of a Viterbi decoder. Terminal 1
The decoded signal applied to 04 is applied to the branch metric calculator 201, and the metric increment of the branch connected to the state is calculated for the metric of the "state" designated by the state number generator 202. The state number generator 202 is configured using, for example, a counter. The metric increment of the branch is added by adder 203 to the metric value read from metric store 205 and corresponding to the specified state number. The branch selector 204 is
From the metric values of each branch input from the adder 202, a branch exhibiting a large metric for each state is selected, and the selected metric is stored in the metric memory 2.
05 and output to the synchronous circuit.
The transmission bits corresponding to the branches selected by the branch selector 204 are stored in the path memory 206, and the transmission bits corresponding to the converged branches are output to the terminal 101.

FIG. 2 is a block diagram showing an example of an encoder for a Viterbi decoder. Constraint length 3, coding rate 1/
2 shows a convolutional encoder. Digital signals applied to the terminal 301 are sequentially stored in shift registers 302 to 304 for each input signal. The outputs of the shift registers 302, 303, 304 are applied to a first exclusive logic circuit 305, the output of which is output to a terminal 306. Shift register 302,3
The output of 04 is applied to the second exclusive logic circuit 307, and its output is output to the terminal 308. The signals at terminals 306 and 308 become convolutional codes. This convolutional code may be transmitted as is as a two-column digital signal, or may be converted into a serial signal by a parallel-to-serial converter 401 shown in the block diagram of FIG. 3 and then transmitted. The signals at terminals 306 and 308 in FIG. 2 are respectively 40 in FIG.
6,408, parallel to series converter 401
The signal is converted into a serial signal and output to the terminal 402.

FIGS. 4a, b, and c are conceptual diagrams showing how synchronization occurs when transmitted as a serial signal. A in the figure shows a signal applied to the terminal 301, and a new digital signal is applied every 2T. FIG. 3b shows a signal at the terminal 402 that has been convolutionally encoded and converted into a serial signal by the parallel/serial converter shown in FIG.
Since the coding rate is 1/2, a digital signal is output every T. On the receiving side, the b signal must be correctly applied to the Viterbi complex as one word every 2T. If 1 as shown in figure c
If the word separation is shifted by T, each word becomes (1', 2),
(2', 3)..., and the original words (1, 1'), (2,
2') Because Viterbi decoding is performed using a word structure different from . . . , correct decoding results will not be obtained. Note that even when the signals of terminals 306 and 308 in FIG. 2 are transmitted in parallel, on the receiving side,
(terminal 308) is not received correctly on the pair (terminal 308).
8, terminal 306), it will not be decoded correctly.

The signal at the terminal 402 is applied to the terminal 100 in FIG. 1 through a transmission path, but by observing whether there is a path between the states with the maximum metric as in the present invention, the word structure can be correctly constructed. , that is, the ability to determine synchronization will be explained using a case where the signal-to-noise ratio is good as an example.

Figures 5a and 5b show trellis diagrams of the Viterbi decoder. FIG. 5a is an example of a trellis diagram in the case of synchronization, and FIG. 5b is an example of the trellis diagram in the case of non-synchronization. In FIG. 5, the black dots indicate the "state" with the maximum metric, and the thick line indicates the path selected with respect to the maximum metric. In the case of synchronization, the trellis of paths regarding the maximum metric is continuous, as shown in Figure 5a.
The maximum metric is the maximum value that the branch metric can take. If this is not synchronized,
This is almost equivalent to the case where the error in the transmission path is 50%, and as shown in FIG. 5b, the trellis of the maximum metric is often not continuous. If the trellis is not continuous in this way, it means that the metric of the next "state" connected to the "state" with the non-maximum metric becomes the maximum at the next time slot. Therefore, when the states are synchronized, the percentage of paths that exist between the "states" with the maximum metric is large, and when they are not synchronized, the percentage is small. Therefore, if the output of the path determination circuit 40 is integrated by the integrator 50 and the fluctuation component is removed, we get
Synchronization or non-synchronization can be determined by a threshold circuit 60 having an appropriate threshold value. That is, in the threshold circuit 60, if the output of the integrating circuit is smaller than the threshold Vth, the threshold circuit 6
0 outputs an identification signal. The identification signal is the phase shifter 1
It becomes a phase shift amount control signal relative to 0, and changes the output phase of the phase shifter 10.

FIGS. 6 and 7 are block diagrams showing first and second embodiments of phase shifter 10, respectively.
In FIG. 6, the decoded signal at terminal 100 is transmitted to phase shift element 6.
01 and output to terminal 104. The word synchronization signal at terminal 105 is sent directly to terminal 10.
6, and the relative time relationship between the signal to be combined and the word synchronization signal is adjusted. In Figure 7, terminal 100
The decoded signal of is output as is to the terminal 104,
The word synchronization signal at terminal 105 is phase-shifted by phase shift element 701 and output to terminal 106 .

The above explanation has proceeded on the assumption that the signal to be decoded is a serial signal, but if the Viterbi decoder is designed to input parallel signals, Figure 8 shows that the input signals to the Viterbi decoder are parallel signals. FIG. 3 is a block diagram showing an example of a phase shifter in the case where the phase shifter shown in FIG. Terminal 801, 8
An equivalent phase shift can be performed by making the signals of 02 interchangeable with switches 803 and 804 and outputting them to terminals 806 and 807. The switching signal of the switch is applied to terminal 805.

Although this embodiment has been described as synchronizing with a convolutional code with a coding rate of 1/2, it is clear that the present invention can also be applied to cases with other coding rates. Furthermore, when the encoded signal is multiphase phase modulated and transmitted, find the carrier phase that has the highest proportion of paths even when there is uncertainty between the "states" that have the maximum metric in the carrier phase. This allows carrier phase uncertainty to be removed.

As described above in detail, the synchronizer circuit of the Viterbi decoder according to the present invention enables word synchronization in the Viterbi decoder itself without using a synchronization signal from an external system.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an example of a synchronization circuit according to the present invention and a Viterbi decoder to which the same is added, Fig. 2 is a block diagram showing an example of a convolutional encoder, and Fig. 3 is a parallel-to-serial converter. FIGS. 4a, b, and c are conceptual diagrams for explaining input and output signals of the convolutional encoder, and FIGS. 5a and b are trellis diagrams of paths. 6 to 8 show examples of phase shifters, respectively. In the figure, 10 is a phase shifter, 20 is a maximum metric judgment circuit, 30 is a register, 40 is a path judgment circuit, 50 is an integrator, 60 is a threshold circuit, 10
3 indicates phase shift amount control terminals, respectively.

Claims (1)

[Claims] 1 a decoded signal input terminal, a first output terminal for decoded signals, a second output terminal for a state number representing a possible internal state, and a third output terminal for a metric value corresponding to the state of the state number. A synchronous circuit for a Viterbi decoder having a phase shifter having a phase shift amount control terminal and changing the phase of a decoded signal input to a decoded signal input terminal of the Viterbi decoder; A circuit that inputs each metric value from the third output terminal and determines the maximum metric among them, and a storage circuit that stores the state number of the state having the maximum metric from the second output terminal, are different. a path determination circuit that determines whether a path exists between states corresponding to each maximum metric determined at a time; an integrator that receives the output of the determination circuit as an input; A Viterbi decoder comprising: a threshold circuit that supplies an identification signal to the phase shift amount control terminal, which is output when the value is less than or equal to a predetermined value or greater than or equal to a predetermined value. synchronous circuit.