JPH038141B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronization circuit for a Viterbi decoder.

In digital communications, one of the methods for reducing transmission errors is a Viterbi decoder. The operation of the Viterbi decoder was reported in March 1973 by the U.S. I.I.
Proceedings of the I.I.I.
The Viterbi Algorithm is described in detail in the paper ``The Viterbi Algorithm,'' published in Volume 61, Issue 3, pages 268 to 278 of the IEEE.

In order to operate the Viterbi decoder, on the transmitting side, a transmission code is encoded using a predetermined method and then transmitted as a code word. On the receiving side, codewords are extracted in synchronization with the encoding on the transmitting side and input to the Viterbi decoder. Conventionally, a synchronization signal from an external system, such as a PCM frame synchronization signal, has been used for this synchronization. however,
This conventional method has a disadvantage in that the format of the synchronization signal differs depending on the system, and therefore the synchronization circuit must be designed for each system. Furthermore, it has been difficult to apply the Viterbi decoder to systems where it is difficult to obtain a frame synchronization signal.

An object of the present invention is to eliminate the drawbacks of the conventional method and provide a synchronization circuit that can synchronize code words in the Viterbi decoder itself.

The configuration and operating principle of the present invention will be explained in detail below using the drawings.

FIG. 1 is a block diagram showing an embodiment of a Viterbi decoder to which an embodiment of the synchronization circuit of the present invention is added. The decoded signal input to the terminal 100 is applied to the decoded signal input terminal 104 of the Viterbi decoder 200 through the phase shifter 10. A decoded signal is output to the terminal 101. The metric value of the Viterbi decoder 200 is input to the metric increment calculation circuit 20 of the synchronization circuit of the present invention. The metric increments are applied to an integrator 30 and integrated.
The integrated output of the integrator 30 is applied to a maximum value determination circuit 40. The maximum value determination result is applied to the phase memory 50, and the phase memory stores the phase at the time of the rarest value determination. The output of phase memory 50 is applied to one selected terminal of switch 70. A selection terminal of the switch 70 is connected to a phase shift amount control terminal 103 of the phase shifter 10. Switching signal generator 60 applies a phase shift control signal to maximum value determiner 40, phase memory 50, and other selected terminals of switch 70, and generates a switching signal for switch 70.

As shown in the example below, the transmission code for Viterbi decoding is such that for each information bit that is sequentially input to the transmitter, multiple bits that depend on multiple past information bits are sequentially output as output bits. Therefore, a synchronization signal (hereinafter referred to as a single word synchronization signal) is applied to terminal 102 to indicate the division of the plurality of bits. The word synchronization signal is outputted to the terminal 105 through the phase shifter 10,
The signal is supplied to a Viterbi decoder 200.

A portion 200 surrounded by a broken line in FIG. 1 shows the basic configuration of a Viterbi decoder. terminal 1
The decoded signal applied to 04 is applied to a branch metric calculator 201, and a metric increment is calculated for each possible branch. The metric increment for each branch is added by adder 202 to the metric value for each state successively retrieved from metric store 204 . The branch selector 203 selects a branch showing a large metric for each state from the metric values of each branch input from the adder 202, supplies the selected metric to the metric storage 204, and outputs it to the synchronization circuit. do. The branches selected by the branch selector 203 are stored in the path memory 205, and converged branches are output to the terminal 101.

FIG. 2 is a block diagram showing an example of an encoder for a Viterbi decoder. A convolutional encoder with a constraint length of 3 and a coding rate of 1/2 is shown. Digital signals applied to the terminal 301 are sequentially stored in shift registers 302 to 304 for each input signal. The outputs of the shift registers 302, 303, and 304 are applied to a first exclusive OR circuit 305, and its output is output to a terminal 306. shift register 30
The output of 2,304 is the second exclusive OR circuit 30
7, and its output is output to terminal 308. The signals at terminals 306 and 308 become convolutional codes. This convolutional code may be transmitted as is as a two-column digital signal, or may be converted into a serial signal by a parallel-to-serial converter 401 shown in the block diagram of FIG. 3 and then transmitted. The signals at terminals 306 and 308 in FIG.
It is applied to the terminals 403 and 404 in the figure, and is converted into a serial signal by the parallel/serial converter 401, and is applied to the terminal 4.
02. Figures 4a, b, and c show how synchronization occurs when transmitted as a serial signal. A in the figure shows a signal applied to the terminal 301, and a new digital signal is applied every 2T. FIG. 3b shows a signal at the terminal 402 that has been convolutionally encoded and converted into a serial signal by the parallel/serial converter shown in FIG. Since the coding rate is 1/2, a digital signal is output every T. On the receiving side, the signal b must be correctly applied to the Viterbi decoder as one word every 2T. If the division of one word is shifted by T as shown in Figure c, each word will be (1',
2), (2', 3)..., and the original word (1, 1'),
Since Viterbi decoding is performed using a word structure different from (2, 2')..., correct decoding results cannot be obtained.

Note that even when the signals of terminals 306 and 308 in Fig. 2 are transmitted in parallel, the receiving side (terminal 3
If a pair such as (terminal 308, terminal 306) is received correctly, it will not be correctly decoded.

Metric increment calculation circuit 20 of the embodiment shown in FIG.
Then, the maximum metric increase is calculated from the new metric value selected by the branch selection circuit 203.
First, the maximum metric value is determined by the maximum metric determination circuit 21 that determines the maximum metric, and one time slot (2T) stored in the register 23 is determined.
A subtracter 22 calculates the difference from the previous maximum metric. Since this value is the maximum metric increase, this value is output to the integrator 30. Thereafter, the contents of the maximum metric determination circuit 21 are transferred to the register 23 in preparation for the next calculation.

The fact that synchronization can be determined by observing the increase in the maximum metric as in the present invention will be explained using a case where the signal-to-noise ratio is good as an example. Figures 5a and 5b show trellis diagrams of the Viterbi decoder. Fifth
Figure a is an example of a trellis diagram in the case of synchronization, the fifth
Figure b is an example of a trellis diagram in the case of no synchronization.

In FIGS. 5a and 5b, black dots indicate the state with the maximum metric, and thick lines indicate the path selected with respect to the maximum metric. In the case of synchronization, the trellis of paths regarding the maximum metric is continuous, as shown in FIG. 5a, and the maximum metric is the maximum value that the branch metric can take. On the other hand, if it is not synchronized, errors in the transmission path may occur.
This is approximately equivalent to the 50% case, and the trellis of the maximum metric may not be continuous as shown in FIG. 5b. If the trellis is not continuous in this way, it means that the metric connected to the non-maximum metric becomes the maximum in the next time slot, and in this case, the amount of increase in the maximum metric value is equal to the maximum value of the branch metrics. It is often a smaller value. Also, if the trellis is continuous, the branch metric between them is not necessarily the maximum. Therefore, the amount of increase in the maximum metric when synchronized is large, and the amount of increase in the maximum metric when not synchronized is small. Therefore, if the output of the metric increment calculation circuit 20 is integrated by the integrator 30 and the fluctuating component is removed, it is possible to determine whether it is synchronized or not.

FIG. 6 is a diagram showing the amount of increase in the maximum metric when the signal-to-noise ratio is good and when the signal-to-noise ratio is good. When the signal-to-noise ratio is good, the amount of increase in the maximum metric as a whole is larger both when synchronized and when not synchronized, compared to when the signal-to-noise ratio is poor. However, in both cases, the amount of increase in the maximum metric during synchronization is large. Since the signal-to-noise ratio is generally unknown on the receiving side, it is difficult to determine synchronization using a fixed threshold when the signal-to-noise ratio changes significantly.

In the present invention, synchronization is achieved by determining the maximum amount of increase in the metric for all phases and setting the output of the phase shifter 10 to the phase when the value reaches the maximum. Therefore, until synchronization is established, the phases are switched one after another by the signal from the switching signal generator.
Once synchronization is established, the phase is fixed. In this example, the amount of increase in the metric in two possible phases during the period from time t ₀ to t ₂ shown in FIG.
At t ₂ , the phase is fixed at a phase with a large increase.

Assume now that the Viterbi decoder has started operating and is in the process of establishing synchronization. At this time, the switching signal generator 60 generates a signal to turn the switch 70 downward, as shown by the broken line in FIG. 7a. at the same time a
As shown by the solid line, phase control information of phase 1 is sent to 40, 50, and 70 in the interval from _t0 to _t1 .

Note that FIGS. 7a, b, c, and d are conceptual diagrams for explaining synchronous and asynchronous states. The maximum metric increase corresponding to phase 1 is obtained as the output of the metric increment calculation circuit 20. The output of the integrator 30 changes as shown in FIG. 7b. At the final time t ₁ of the interval t ₀ to _{t 1} , the maximum value determiner is the integrator output
It detects m ₁ and stores it as the maximum value, and also issues a signal to store the phase in the phase memory 50. As a result, phase 1 is stored in the phase memory.

Next, in the period from t ₁ to _{t 2} , the switching signal generator sends out phase 2 signals to 40, 50, and 70. The integrator output changes as shown in FIG. 7b in accordance with the amount of increase in the maximum metric at this time. The maximum value determiner 40 is t ₂
Detect the integrator output m ₂ at the time point and calculate the previous value
It is determined that m ₂ is larger than m ₁ .
The phase memory 50 stores phase 2 based on this determination result.

In this example, the possible phase states of the convolutional code are 2
Therefore, at time _t2 , the above comparison process based on the maximum metric and minimum metric for all phases ends. The switching signal generator is shown in Figure 7a.
As shown by the broken line, a switching signal is generated to turn the switch 70 upward, and the circuit executes Viterbi decoding with phase 2 in the synchronous state.

FIGS. 8 and 9 are block diagrams showing first and second embodiments of phase shifter 10, respectively.
In FIG. 8, the decoded signal at terminal 100 is transmitted to phase shift element 7.
01 and output to terminal 104. The word synchronization signal at terminal 102 is sent directly to terminal 10.
5, and the relative time relationship between the decoded signal and the word synchronization signal is adjusted. In Figure 9, terminal 100
The decoded signal of is output as is to the terminal 104,
The word synchronization signal at terminal 102 is phase-shifted by phase shift element 801 and output to terminal 105.

Although the above description has proceeded on the assumption that the signal to be decoded is a serial signal, there are cases where the Viterbi decoder receives parallel signals as input.

FIG. 10 is a block diagram showing an example of a phase shifter when the input signals to the Viterbi decoder are parallel. Switch 90 switches the signals on terminals 901 and 902.
3,904 makes it replaceable and the terminal 90
Equivalent phase shifting can be performed by outputting to 6,907. The switch switching signal is at terminal 9.
05.

In this embodiment, the amount of increase in the maximum metric was explained as being determined by the metric increment calculation circuit 20, but when the amount of increase in the maximum metric is large, the amount of increase in other metrics is also large, so the amount of increase in the maximum metric is not necessarily the same. The same effect can be obtained by determining synchronization based on the amount of increase in the second largest metric, the third largest metric, or generally the Nth largest metric. It is also clear that the time interval for calculating the increment may also be longer. Furthermore, if a certain value is subtracted from each metric value to prevent metric overflow, it is necessary to supply the metric value before subtraction to the metric increment calculation circuit in order to correctly calculate the amount of metric increase. There is.

Further, although this embodiment has been described as synchronizing with a convolutional code having a coding rate of 1/2, it is clear that the present invention can also be applied to cases of other coding rates. Furthermore, when an encoded signal is transmitted after being subjected to polyphase phase modulation, even if there is uncertainty in the carrier phase, the uncertainty in the carrier phase can be reduced by finding the carrier phase with a large increase in the metric. can be excluded.

As described in detail above, the Viterbi decoder synchronization circuit according to the present invention enables the Viterbi decoder itself to perform word synchronization without using a synchronization signal from an external system.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an example of a synchronization circuit according to the present invention and a Viterbi decoder to which the same is added, Fig. 2 is a block diagram showing an example of a convolutional encoder, and Fig. 3 is a parallel-to-serial converter. Figures 4a, b, and c are conceptual diagrams for explaining the input and output signals of the convolutional encoder, Figure 5 is a path trellis diagram, and Figure 6 shows the amount of increase in metrics. Figure 7a, which shows the change in signal-to-noise ratio of
b, c, and d are diagrams showing signals of each part in FIG. 1, and FIGS. 8 to 10 are block diagrams showing examples of phase shifters, respectively. In the figure, 10 is a phase shifter, 20 is a metric increment calculation circuit, 30 is an integrator, 40 is a maximum value judger, 50 is a phase memory, 60 is a switching signal generator, and 70 is a switch. are shown respectively.

Claims (1)

[Claims] 1 A decoded signal input terminal, a first output terminal for decoded signals, and a second
A synchronous circuit for a Viterbi decoder having an output terminal, the phase shifter having a phase shift amount control terminal and changing the phase of a decoded signal input to a decoded signal input terminal of the Viterbi decoder; Input the metrics of each internal state output from the second output terminal of the decoder, count from the largest one to determine the Nth metric of a constant natural number, and calculate the difference between the Nth metric at different times. a metric increment calculation circuit; an integrator that receives the output of the metric increment calculation circuit; a maximum value determiner that receives the output of the integrator; and a phase memory that stores the phase when determining the maximum value. , a switch for inputting the output of the phase storage device as an input signal to one selected terminal and connecting the selection terminal to a phase shift amount control terminal of the phase shifter; and a switching signal generator that supplies a switching signal to another selected terminal of the switch and outputs a switching signal for the switch.