JPH0160977B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronization circuit for a Viterbi decoder.

In digital communications, one of the methods for reducing transmission errors is a Viterbi decoder. The operation of the Viterbi decoder was reported in March 1973 by the U.S. I.I.
The paper described on pages 268 to 278 of Volume 61, No. 3 of Proceedings of the IEEE, published by IEEE. The Viterbi Algorithm
Algorithm).

In order to operate the Viterbi decoder, on the transmitting side, a transmission code is encoded using a predetermined method and then transmitted as a code word. On the receiving side, codewords are extracted in synchronization with the encoding on the transmitting side and input to the Viterbi decoder. Conventionally, a synchronization signal from an external system, such as a PCM frame synchronization signal, has been used for this synchronization. however,
This conventional method has the disadvantage that the synchronization circuit must be designed for each system because the formation of the synchronization signal differs from system to system. Furthermore, it has been difficult to apply the Viterbi decoder to systems where it is difficult to obtain a frame synchronization signal.

The purpose of the present invention is to eliminate the drawbacks of the conventional method and provide a synchronization circuit that can synchronize code words in the Viterbi decoder itself and can synchronize correctly even if the signal-to-noise ratio of the transmission path changes. It is something to do.

The configuration and operating principle of the present invention will be explained in detail below using the drawings.

FIG. 1 is a block diagram showing an embodiment of a Viterbi decoder to which a synchronization circuit according to the present invention is added. The decoded signal input to the terminal 101 is applied to the decoded signal input terminal 104 of the Viterbi decoder 103 through the phase shifter 102 . The decoded signal is output to the terminal 115. The maximum/minimum metric selector 105 receives metrics of possible internal states from the Viterbi decoder. Terminal 106,1
The maximum metric value and minimum metric value outputted to 07 are applied to a subtracter 108, and the subtracted output is applied to an integrator 109 for integration. The integrated output of the integrator 109 is applied to the maximum value determiner 110. The maximum value determination result is applied to the phase memory 111, and the phase memory stores the phase at the time of maximum value determination. The output of the phase memory 111 is sent to the switch 112.
is applied to one selected terminal of. switch 11
The selection terminal 2 is the phase shift amount control terminal 1 of the transfer device 102.
14. The switching signal generator 113 transfers the transfer control signal to the maximum value determiner 110 and the phase memory 11.
1 and other selected terminals of switch 112, and generates a switching signal for switch 112.

As shown in the example below, the transmission code for Viterbi decoding is such that for each information bit that is sequentially input to the transmitter, multiple bits that depend on multiple past information bits are sequentially output as output bits. It consists of A synchronization signal to indicate the division of these multiple bits (hereinafter simply referred to as a word synchronization signal)
is applied to terminal 116, outputted to terminal 117 through phase shifter 102, and supplied to Viterbi decoder 103.

A portion 103 surrounded by a broken line in FIG. 1 shows the basic configuration of a Viterbi decoder. terminal 1
The decoded signal applied to 04 is applied to a branch metric calculator 131, and a metric increment is calculated for each possible branch. Adder 132 adds the metric increment for each branch to the metric value for each state read from metric store 134 . The branch selector 133 selects a branch exhibiting a large metric for each state from the metric values of each branch input from the adder 132, supplies the selected metric to the metric storage 134, and outputs it to the synchronization circuit. do. The branches selected by the branch selector 133 are stored in the path memory 135, and converged branches are output to the terminal 105. Metric storage 13
The contents of 4 are normalized by the metric normalization circuit 136 to prevent overflow.

FIG. 2 is a block diagram showing an example of an encoder for a Viterbi decoder. Constraint length 3, coding rate 1/
2 shows a convolutional encoder. The digital signals applied to the terminal 201 are sequentially stored in shift registers 202 to 204 for each input signal. The outputs of the shift registers 202, 203, and 204 are applied to a first exclusive OR circuit 205, and its output is output to a terminal 206. shift register 202,
The output of 204 is applied to a second exclusive OR circuit 207, and its output is output to a terminal 208.
The signals at terminals 206 and 208 become convolutional codes.
This convolutional code may be transmitted as it is as a two-column digital signal, or may be sent upstream to a parallel/serial converter 303 shown in the block diagram of FIG. 3, where it is converted into a serial signal and transmitted. The signals at terminals 206 and 208 in FIG. 2 are respectively applied to terminals 301 and 302 in FIG.
is output to.

FIGS. 4a, b, and c are conceptual diagrams showing how synchronization occurs when transmitted as a serial signal. A in the figure shows a signal applied to the terminal 201, and a new digital signal is applied every 2T. FIG. 3b shows a signal at the terminal 304 that has been convolutionally encoded and converted into a serial signal by the parallel/serial converter shown in FIG.
Since the coding rate is 1/2, a digital signal is output every T. On the receiving side, the signal b must be correctly applied to the Viterbi decoder as one word every 2T. If 1 as shown in figure c
If the word separation is shifted by T, each word becomes (1', 2),
(2', 3)..., and the original words (1, 1'), (2, 2'
)
Since Viterbi decoding is performed using a word structure different from the word structure, correct decoding results cannot be obtained. Note that even when the signals of the terminals 206 and 208 in FIG.
If a pair such as terminal 206) is formed, it will not be decoded correctly.

Now, the signal at terminal 302 is transmitted to terminal 101 in FIG.
Suppose that it is applied to In the Viterbi decoder, when word synchronization is not achieved, the difference between the maximum metric and minimum metric is small, as shown in FIG. 5, and when word synchronization is achieved, this difference widens.
Assume now that the Viterbi decoder has started operating and is in the process of establishing synchronization. At this time, the switching signal generator 113 generates a signal to turn the switch 112 downward. At the same time, as shown by the solid line in Figure 6a, t ₀
The phase control signal of phase 1 is set to 110 to 1 in the interval of ~t ₁ .
Send on 12th. Note that FIGS. 6a, b, c, and d are conceptual diagrams for explaining synchronous and asynchronous states. The maximum metric and minimum metric corresponding to phase 1 appear at terminals 106 and 107, and their difference signal appears at the output of subtractor 108. The output of the integrator 109 changes as shown in FIG. 6b. section
At the final time point t1 of _t0 to _t1 , the maximum value determiner detects the integrator output _m1 , stores this as the maximum value _, and issues a signal for storing the phase in the phase memory 111. As a result, phase 1 is stored in the phase memory.

Next, in the interval t ₁ to _{t 2} , the switching signal generator sends out phase 2 signals to 109 to 112. Integrator 109
is reset when the switching signal generator output changes. The integrator output changes as shown in FIG. 6b depending on the maximum metric and minimum metric at this time. The maximum value determiner detects the integrator output m ₂ at time t ₂ and compares it with the previous value m ₁ to determine that m ₂ is larger. The phase memory 111 stores phase 2 based on this determination result.

In this example, the possible phase states of the convolutional code are 2
Therefore, at time _t2 , the above comparison process based on the maximum metric and minimum metric for all phases ends. The switching signal generator generates a switching signal that turns switch 112 upward, and the circuit synchronizes phase 2 and performs Viterbi decoding.

As described above, in the present invention, the magnitude of the difference between the maximum metric and the minimum metric is compared for all possible phase states of the convolutional code, and the phase showing the maximum value is determined to be the synchronized phase. Therefore, it is possible to correctly synchronize even when the difference between the maximum and minimum metrics in the synchronous and asynchronous states changes as the signal-to-noise ratio of the transmission path changes, making it difficult to determine synchronous or asynchronous using a fixed threshold. Can be done.

7 and 8 are block diagrams showing first and second embodiments of phase shifter 102, respectively. In FIG. 7, the decoded signal at terminal 101 is phase-shifted through phase shift element 701 and output to terminal 104. The word synchronization signal at terminal 116 is sent directly to terminal 1.
17, and the relative time relationship between the decoded signal and the word synchronization signal is adjusted. In Figure 8, terminal 10
The decoded signal of 1 is output as is to the terminal 104, and the word synchronization signal of the terminal 116 is phase-shifted by the phase shift element 801 and output to the terminal 117.

Although the above explanation has proceeded on the assumption that the signal to be decoded is a serial signal, there are cases where the Viterbi decoder receives parallel signals as input.

FIG. 9 is a block diagram showing an example of a phase shifter when the input signals to the Viterbi decoder are parallel.
Switch the signals of terminals 901 and 902 to switches 903 and 9
04, terminals 906 and 90 can be replaced.
Equivalent phase shifting can be performed by outputting to 7. The switching signal of the switch is applied to terminal 905.

In addition, although the above explanation is based on the case of convolutional encoding with a coding rate of 1/2, it can of course be applied to cases with other coding rates. Even when the carrier wave phase is uncertain when it is transmitted after being subjected to polyphase phase modulation, the possible states of the carrier wave phase can be synchronized by comparing the maximum metric and the minimum metric mentioned above. Needless to say.

As described above in detail, the Viterbi decoder synchronization circuit according to the present invention enables word synchronization in the Viterbi decoder itself without using a synchronization signal from an external system.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an example of a synchronization circuit according to the present invention and a Viterbi decoder to which the same is added, Fig. 2 is a block diagram showing an example of a convolutional encoder, and Fig. 3 is a parallel-to-serial converter. Figures 4a, b, and c are conceptual diagrams for explaining the input and output signals of the convolutional encoder, and Figure 5 is a conceptual diagram for explaining changes in the maximum and minimum metrics due to synchronization and asynchrony. Conceptual diagram, Figure 6 a, b, c, d
FIG. 1 is a conceptual diagram for explaining signals of each part in the circuit, and FIGS. 7 to 9 are block diagrams showing examples of phase shifters. In the figure, 102 is a phase shifter, 105 is a maximum/minimum metric selector, 106 and 107 are maximum metric and minimum metric output terminals, respectively.
08 represents a subtracter, 109 represents an integrator, 110 represents a maximum value determiner, 111 represents a phase memory, 112 represents a switch, and 113 represents a switching signal generator.

Claims (1)

[Claims] 1. In a Viterbi decoder having a composite signal input terminal, a composite signal output terminal, and an output terminal for metrics of possible internal states, a phase shifter having a phase shift amount control terminal for shifting the phase of the input signal; A maximum/minimum metric selector that inputs the metric of each internal state and outputs its maximum and minimum values; a subtracter that receives the maximum metric and minimum metric as two input signals; An integrator that resets and integrates the contents every time the input phase changes in the phase shifter, and a maximum value that uses the integrator output immediately before reset as an input signal and determines the maximum value among the integrator outputs corresponding to each phase. a determiner, a phase memory for storing the phase at the time of the maximum value determination, and an output of the phase memory as an input signal to one selected terminal, which is stored in the phase memory after the maximum value determination. A switch that connects the phase at the time of maximum value determination to the phase shift amount control terminal of the phase shifter as a selection terminal output, and a switch that connects the phase shift control signal to the maximum value determination device, the phase memory, and another selected one of the switches. a switching signal generator that supplies a switching signal to a terminal and outputs a switching signal for the switch, the decoding signal is used as an input signal of the phase shifter, and the output signal of the phase shifter is used as an input signal of the Viterbi decoder. A synchronization circuit for a Viterbi decoder featuring: