JPH02170726A - Viterbi demodulating circuit - Google Patents

Abstract

PURPOSE:To reduce energy consumption by using a path selective circuit, detecting a path connecting all stages, and determining a finally selected encoding bit. CONSTITUTION:The bit corresponding to state transition out of the outputs of an ACS circuit is inputted to a path display circuit as a signal successively and circulatively selected by the ACS circuit. Since an input signal 3 indicates the state of a previous time slot concerning the path at maximum likelihood for the respective states, the state of the path display circuit on the previous stage is selected from the contents of a path memory cell with the use of the path selective circuit, and by repeating the processing up to the final stage, the contents of the path display circuit on the final stage is made into an output signal 4. Consequently, without storing a redundant bit, the selected encoding bit can be obtained. Thus, the energy consumption can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is used in a digital signal transmission system, and particularly relates to a Viterbi decoding circuit for error correcting convolutionally encoded signals.

[Conventional technology]

A block diagram of a conventional convolutional encoder and Viterbi decoder is shown in FIG. The convolutional encoder convolutionally encodes M-sequence signals to produce N-sequence encoded signals. A branch metric generator (BMG) calculates the likelihood of each received signal,
The ACS circuit selects the most likely state transition for each state of the encoder. Here, each state of the encoder means the contents of 2 (ki constraint length) memories in the encoder, and when an encoder with a constraint length is used, there are 2 types of states. A state transition is a transition from a certain state to the next state when a certain input signal is received.

FIG. 6 shows a convolutional encoder with a constraint length of 3 and a coding rate of 1/2, and FIG. 7 shows an example of its state transition diagram.

The encoder consists of two shift registers SR and one exclusive OR circuit. In this diagram, time is shown in the horizontal direction, and states are shown in the vertical direction. Lines connecting states at each time point indicate state transitions.

In the Viterbi decoding circuit, the signal output from the ACS circuit is input to the path memory. FIG. 8 shows a configuration diagram of the path memory, and FIG. 9 shows the configuration of the path memory cell. In the figure, for simplicity, the number of states is 4 and the number of trunks is 3. However, generally, the truncation is about five times the constraint length.

In the path memory, input symbols are stored and selected over T time slots (T: truncation). When the encoder input is m, m2''T memory areas are required as the path memory circuit.

In addition, in the path memory circuit, for each state, 2''' of the memory contents of the previous stage are connected to the next stage, and the one with the largest likelihood is selected. Therefore, there are 2'T of 1/2" selectors. It becomes necessary.

However, in the conventional circuit configuration as described above, when the constraint length k and the number m of encoder input bits to be transmitted become large, the path memory circuit becomes dramatically large. Path memory is likened to a shift register, and in order to transition the stored contents, it is necessary to operate all the registers every clock, which increases power consumption, and requires a transition network for the number of bits to be stored, which reduces the amount of wiring. The disadvantage is that it becomes large.

Next, coded modulation will be explained. A block diagram of the encoder and decoder of the conventional coded modulation method is shown in FIG.
(G, Ungerboeck ”Channel c
oding with ＋＊ulti 1level/p
hase signals”1EEE Trans,
onInformation Theory + vo
l, IT 28. NcLl, pp55-67+Jan
1982) In coded modulation, M sequences of (K + M) sequence information signals are convolutionally encoded to produce N sequence encoded signals, and then a mapping circuit (MAP) which receives these (K + N) sequence signals as input Transmission symbols are optimally arranged on the signal space so that the minimum intersymbol distance is maximized. J!
The properly placed signals are multi-level modulated by a modulator (MOD). The modulated signal is transmitted, received at the receiving end, and then demodulated by a demodulator (DEM). On the decoder side, a demapping circuit (DEMAP) performs the inverse calculation of the mapping circuit, a branch metric generator (BMG) calculates the likelihood of each received symbol, and an ACS circuit calculates the likelihood of each received symbol. Select a suitable symbol. In the conventional path memory, a bit corresponding to the state a transition of the output of the ACS circuit is input and stored. Here, the redundant bits out of the convolutional encoder output are not directly needed to obtain the final decoded signal and are therefore not stored in the path memory. However, in the coded modulation method shown in Fig. 10,
In addition to coded bits, non-coded bits also need to be stored as path memory inputs.

[Means for Solving the Problems] The present invention uses a path selection circuit to detect connected paths through all stages and finally determine the selected encoded bit.

The purpose of this invention is to reduce power consumption and circuit size.

〔Example〕

FIG. 1 shows a block diagram of an embodiment of the invention.

In the figure, 3 is the output from the ACS circuit, which is information corresponding to state transition, 1 is the write clock for latching 3 in the start stage of the path memory, and 2 is the readout for reading the decoded output from the final stage of the path memory. 4 is a clock, 4 is a decoded output, 5 is a state transition network connecting stages of the path selection circuit, 6 is a path selection signal indicating the selected path, 7
indicates a path selection signal from the path memory.

FIG. 2 shows an example of the configuration of the path display circuit. 1.2°3.4
, 6.7 correspond to each signal in FIG. Reference numeral 8 denotes a circuit that outputs a redundant bit unique to the state number, and in this configuration example, it is provided only for the state where the redundant bit becomes "1".

FIG. 3 shows an example of the configuration of the path selection circuit. l, 5°6.7
correspond to each signal in FIG. Figure 4 shows 1.2 in Figure 1.
shows the timing relationship of the signals. The write clock is
1 in Figure 1. The read clock corresponds to 2.

Bits corresponding to state transitions among the outputs of the ACS circuit are sequentially and cyclically input to the bus display circuit as signals selected by the ACS circuit. This input signal will indicate the most likely state of the previous time slot for the bus for each state. Therefore, by sequentially selecting the state of the bus display circuit at the previous stage from the contents of the path memory cells and repeating this process until the final stage, the contents of the bus display circuit at the final stage become the signal to be output. This is a function to select surviving buses based on the contents.

Each path memory cell has a bus display circuit, where the ACS
Memorize the output of the circuit. One of the states of the next stage is selected from the contents of the bus display circuit of any state of the first stage, and a selection pulse is sent to the path selection circuit of that state.

The path selection circuit to which the selection pulse has been sent further selects one of the next-stage states based on the contents of the bus display circuit. Repeat this until the final step. The decoded output corresponding to the selected path is determined from the contents of the final bus display circuit. In the bus display circuit of FIG. 2, the output of the ACS circuit is memorized in the frimbflop. Furthermore, a logic circuit generates a decoded signal corresponding to the memory contents.

In the bus selection circuit of FIG. 3, when a selection pulse is sent, or when the stage is the first stage, a selection pulse is sent to one state selected according to the contents of the bus display circuit.

Furthermore, the state of the final stage indicates redundant bits in the output of the convolutional encoder. As shown in the encoder of FIG. 6, the redundant bits output from the encoder become the output of the final stage of the shift register in the encoder. Furthermore, since the state corresponds to the contents of the shift register of the encoder, once the state is determined, the redundant bits are also determined.

From the above, by using the circuit described above to determine the state of the final stage and its bus display circuit, the encoded bits to be selected can be determined without storing redundant bits.

(Effect of the invention〕 The features of this invention include the following points.

(1) Among the 92 stages of bus memo, only one stage operates at the same time while the other stages are held, reducing power consumption to about 1/p.

(Regardless of the number of bits input from the 21ACS circuit, the transition network only requires one bit, so the gate
The amount of power consumption wiring can be reduced. In the conventional type, multiple bits are required to send the number of bits corresponding to the contents of the bus display circuit.

(3) Signal changes within the bus network occur only in the most recent stage in terms of time, and do not change in the latter half, leading to rock bottom power consumption.

(4) Since the path memory cell is not a shifter type, it can be realized with a latch type instead of a D-type flip-flop, so it can be realized with a small number of transistors.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a path memory cell which is a main part of this invention, FIG. 2 is a diagram showing a bus display circuit in FIG. 1, and FIG. 3 is a diagram showing a bus selection circuit in FIG. 1. Figure 4 is the first
5 is a block diagram showing a convolutional encoder and a Viterbi decoder, and FIG. 6 is a diagram showing a convolutional encoder with a constraint length of 3 and a coding rate of 1/2. 7 is a state transition diagram, FIG. 8 is a diagram showing a conventional path memory, FIG. 9 is a diagram showing a conventional path memory cell, and FIG. 10 is a diagram showing a conventional coded modulation method encoder. and a block diagram showing a decoder. Patent applicant Nippon Telegraph and Telephone Corporation

Claims (1)

[Claims] (1) On the transmitting side, a branch metric generation circuit takes as input the signal encoded by the convolutional encoder and calculates the likelihood of each received signal, and the output of the branch metric generation circuit takes as input the signal encoded by the convolutional encoder and calculates the likelihood of each state. In a Viterbi decoding circuit consisting of an ACS circuit that selects state transitions and a path memory circuit that receives the output of the ACS circuit and stores paths in p time slots, the path memory circuit includes p storage circuit groups and a path selection circuit. In the memory circuit group, at time t, only the first memory circuit inputs the output of the ACS circuit at the same time and newly stores this input, and the other memory circuits input the output at time t-1.
A Viterbi decoding circuit characterized in that the previous storage contents are retained as they are, and the path selection circuit has a function of receiving the contents of the p storage circuit groups as input and selecting a surviving path.