KR0169680B1 - Vitervi decoder - Google Patents

Abstract

The present invention relates to a Viterbi decoder, the Viterbi decoder of the present invention is a general Viterbi decoder composed of the branch length calculation unit 100, the ACS unit 200 and the path storage unit 300, the ACS unit ( 200 is an adder 210 and a first latch unit 220, a comparison selector 230, a second latch unit 24, a shift converter 250, a third latch unit 260, and a multiplexing unit. (270): and the fourth latch unit 280, and in the case of 4-state by designing to implement a single ACS unit of the component block of the Viterbi decoder, when implementing the ACS unit as a specific application integrated circuit (ASIC) This has the advantage that the chip area can be reduced.

Description

Viterbi Decoder

(A) and (b) of FIG. 1 are trellis diagrams for Viterbi decoding.

2 is a block diagram of a general Viterbi decoder.

3 is a block diagram of an ACS unit of a Viterbi decoder according to the present invention.

4 is a detailed block diagram of the shift conversion unit shown in FIG.

5 is a four-state trellis diagram.

FIG. 6 is a timing diagram of the ACS calculator shown in FIG.

* Explanation of symbols for main parts of the drawings

200: ACS unit 210: adder

210-1: first adder 210-2: second adder

220: first latch portion 220-1: first latch

220-2: second latch 230: comparison selection unit

240: second latch portion 250: shift converting portion

250-1: first multiplexer 250-2: latch

250-3: second multiplexer 260: third latch unit

270: multiplexer 270-1: first multiplexer

270-2: second multiplexer 280: fourth latch portion

280-1: first latch 280-2: second latch

The present invention relates to a Viterbi decoder. In particular, the calculated branch metrics are input to the previous path metric value, and the path length value among the paths that meet each other is deleted. The Viterbi decoder simply implements the part that selects only the remaining path length value.

Convolution decoding refers to decoding a codeword sequence encoded by a convolutional coding scheme to reproduce a bit sequence, that is, a message bit sequence before being encoded.

In convolutional decoding, a maximum likelihood decoding (MLH) method is used. The maximum decoding method is a method of decoding a sequence received by a receiver under the assumption that an error occurs on a transmission line during transmission of a digital signal.

If a codeword modulated by a carrier, that is, a digital signal, is input to the receiver, the demodulator demodulates the codeword sequence, and when the codeword sequence is input to the decoder, the codeword is compared with all codewords that can be transmitted from the transmitter. A similar comparison codeword is selected to assume that the comparison codeword is an error free codeword transmitted from the transmitter and to reproduce the message bits by this selected codeword. The most similar decoding method (MLH) is referred to as the received codeword is compared with the comparison codeword to select and decode the most similar one.

In more detail, the maximum approximation decoding method MLH is a codeword having a predetermined length, that is, a code, that is not transmitted one bit after decoding each input code word. After comparing all lengths of a sequence, a sequence of the most similar comparison codewords is selected, and a message bit sequence corresponding to the sequence of comparison codewords is output.

Therefore, it is necessary to store all information generated during the comparison of one codeword sequence until one comparison codeword sequence is selected.

To illustrate the maximum approximate decoding scheme (MLH), assume that the message bits are encoded by an encoder with a 1/2 code rate at the transmitter.

Therefore, the encoder outputs a code word composed of two bits by one message bit.

If a codeword sequence composed of codewords is modulated by a modulator to add noise to each bit constituting a codeword sequence independently of each other during transmission, that is, adds additive gaussian white noise (AGWN). Errors can occur in the codeword sequence. Therefore, if the codeword sequence having an error is decoded as it is, an error occurs in the message bit. If the status of the shift register of the encoder is 000, the codeword of two states is output according to the input bit contents. If the message bit is 0, the codeword is 00.1, and the codeword is 11.

In this case, if the codeword 11 is output by message bit 1, since the decoder recognizes the shifter register state of the coder in advance when the codeword decoder decodes it, no error occurs in the digital signal in the transmission line. When 11 comes in, it outputs message bit 1 correctly. However, if an error occurs during transmission of a digital signal and the output 11 of the encoder is changed to 01 and input to the decoder, the decoder cannot decode 01 and thus cannot reproduce the message bit with 1, causing an error in the message bit.

Also, if the codeword input to the decoder is changed to 00 instead of 11, the decoder considers the message bit to be 0 and outputs an error in the message bit. Therefore, to prevent this, all received codeword sequences having a constant length are compared with all codewords that can be output from the encoder, that is, four codewords of 00, 01, 10, and 11 at a 1/2 code rate. Selects and decodes the message bits corresponding to this comparison codeword sequence in order to regard it as an error-free received codeword sequence.

Therefore, the maximum approximation decoding method (MLH) must store the code sequence until the received codeword sequence having a predetermined length is completed and the comparison codeword is compared and the most similar comparison codeword is selected and decoded.

In addition, since the received codeword which is continuously input during this period must be stored, all comparison codeword sequences (there are four comparison codewords at 1/2 code rate) until the storage capacity becomes large and the comparison is completed. This complicates the circuit. The Viterbi decoding method is a method of improving the complexity of the maximum approximate decoding method (MLH).

The Viterbi decoding method was developed based on the maximum approximation decoding method (MLH), and greatly reduced the complexity of the maximum approximation decoding method. In Vietbi, the Viterbi decoding algorithm was first developed by An efficient and practical technique for Viterbi decoding was first presented by Heller.

Viterbi decoding is a maximum approximate decoding technique for Forward Error Correcting (FEC) convolutional codes, and has a high random error correction capability in a communication channel, which is suitable for satellite communication.

Error correction of the Viterbi decoder is performed by selecting the codeword closest to the received codeword in all codeword sequences output from the encoder.

The biggest advantage of Viterbi's maximum approximation decoder is that it decodes N message bits. As with the maximum approximation decoder, the operation of the decoder does not increase exponentially with the number of message bits but only increases by N2 ^K-1 . .

In other words, it has a linear relationship with the number of message bits and has an exponential relationship with the singular K of the shift register, so that many K-values cannot be used. Fortunately, this method can fully function even if the K-value is small.

The Viterbi decoding algorithm is an algorithm that performs maximum approximation decoding using trellis diagram. It is a kind of dynamic programming. In the Viterbi decoding algorithm, two paths having different paths are different at some point. When they meet, they compare the hamming distances of these two paths, so that only one path with a short path length, i.e. a low probability of error, and a long double path metric are path memory. It is erased from.

At this time, the remaining path is called a surviving path. The determination of the maintenance path is performed at every point in time. In this case, the path having a long path length can be deleted to avoid the complexity of decryption and to increase the storage capacity.

In this way branch (branch) for the first codeword received at t ₁ at which point a by decoding of codewords of the first t ₁ At this time there is a shared each current remaining path and outputs the first bit of the message bit.

Here, selecting the optimal path is selecting the codeword with the maximum approximation. In 1969, Omura announced that the Viterbi algorithm was actually the maximum approximation algorithm.

(A) and (b) of FIG. 1 show a trellis for Viterbi decoding, and as shown in (a) of FIG. 1, the finite state machie has no path through the trellis. And branch branch λ of the time interval k, k + 1 is calculated due to the transition of the observed state. The maximum approximate path is then calculated recursively by the algorithm.

That is, during decoding, the distance between the code of the branch corresponding to the received signal, that is, the branch length λ, is calculated. This distance serves as a criterion for signal discrimination, which is called a metric. The metric is a hamming distance for hard decision decoding and an Euclidean distance for soft decision decoding.

Referring to (b) of FIG. 1, an optimal path for each of the N nodes at time k is calculated, and a new path metric lambda of nodes S _{1, K + 1} and S _{2, K + 1} is calculated. _{1, K + 1} and λ2 _{, K + 1} are as follows.

_{λ 1, K + 1 = maxium} (λ 11.K + λ 1.K, λ 12.K + λ 2.K)

_{λ 2, K + 1 = maxium} (λ 21.K + λ 1.K, λ 22.K + λ 2.K)

In (b) of FIG. 1, D (survivor depth) refers to the number of time steps that are merged with a very high probability when trace back paths, and the decoding of the Viterbi algorithm in actual implementation. The potential is determined.

2 is a block diagram of a general Viterbi decoder, the branch length calculation unit (100: Branch Metrics Units) for receiving the received data to calculate the length for each branch; Receive the calculated branch length value from the branch length calculation unit 100 and add it to the previous path length value, and delete the long path length value from the two paths that meet each other and only the remaining path length value is small. An ACS unit for selecting (Adder Comparator Selector: hereinafter referred to as ACS) 200; And a path storage unit 300 for storing a maintenance path selected by the ACS unit 200.

A basic operation principle of the Viterbi decoder configured as described above is as follows.

Assume that data entering the input passes continuously in stages.

The branch length calculating unit 100 receives the input data and calculates the length of each branch, that is, the branch length λ _ij.k , which is directly related to the length of the received codeword, that is, the length of the output codeword of the encoder. The larger the number of configuration bits of the codeword, the more complicated the circuit becomes.

For example, if a codeword is composed of 2 bits, a comparison codeword for comparing 2 bits of received codewords is required, that is, ^2, or 4, and if a codeword is composed of 3 bits for 4 comparisons, one received codeword is compared. to branch to the calculated length is ²³ words, it is necessary eoga eight comparison code.

That is, since a codeword consisting of 3 bits has 7 chances of being changed to another codeword during transmission, it must be compared 8 times to receive one codeword.

In addition, the longer the length of the codeword, the larger the resulting value of the branch length than the shorter the length of the codeword. After all, the larger the branch length value, the larger the storage capacity for storing the branch length as the branch length value becomes larger. The ACS unit 200 of the stage becomes complicated.

The ACS unit 200 receives the branch length value calculated by the branch length calculating unit 100 and adds the branch length value to the previous path length value. At this time, the long path length value is deleted from the two paths that meet each other and the remaining path length value is small. Only thing is memorized as a maintenance path.

The ACS feature is 2 ^K-1 shift register (not shown) conditions respectively, that is the ACS unit 2 ^K-1 when I is performed in that each node (node) is required to have a high decoding speed dog, that is that each node Each separate installation requires a high decoding speed, which complicates the ACS device.

Therefore, in order to simplify the decoder, the ACS device should be ideally operated and the circuit constituting the ACS device should be properly designed.

As described above, when the maintenance paths selected by the ACS apparatus are stored in the path storage unit 300 and the path having the smallest path length value is selected in the path storage unit 300 to output a message by the path, the ACS unit 200 Receives a path selection signal for this, decodes the codeword sequence of the corresponding path, and outputs a message bit.

A Viterbi algorithm is used for decoding Trellis Coded Modulation (TCM) signals in high definition television (HDTV), and there is a Viterbi decoder that performs the Viterbi algorithm inside the TCM decoder. When designing the, we need each decoder according to state. That is, separate decoders for 4-state and 8-state are required.

In the four-state case, four ACS units 200 of the general Viterbi decoder shown in FIG. 2 are required. When designing with a specific integrated circuit (ASIC), there is a problem that the area of the chip increases.

Accordingly, the present invention has been made to solve the above problems, in the four-state case, the calculated two branch length value (branch metrics) is added to the previous path length value and two paths that meet each other at this time The goal is to provide a Viterbi decoder that reduces the area of the chip by simply implementing an ACS section that deletes the long path length value and selects only the remaining path length value.

Viterbi decoder of the present invention for achieving the above object, the branch length calculation unit for receiving the received data to calculate the length for each branch, the branch length value calculated from the branch length calculation unit immediately before A general Viterbi decoder consisting of an ACS unit which adds a path length value to the path length value and deletes the long path length value from the two paths which meet each other, and selects only the remaining path length value is small, and a path storage unit which stores the maintenance path selected by the ACS unit. The ACS unit receives the first input signal and the second output signal, adds two signals, receives the second input signal and the first output signal, adds the two signals, and adds the second input signal and the first output signal. An adder for inputting two signals, the first latch unit for latching two addition signals from the adder; A comparison selector for comparing and selecting two input signals from the second selector: a second latch unit for latching a selection signal from the comparison selector: a shift conversion for receiving a signal from the second latch unit and outputting an output signal according to a control signal A third latch unit for latching an input signal from the shift converter; a multiplexer which selects one signal according to a control signal from each of the two input signals and outputs a signal respectively; And a fourth latch unit for outputting a first output signal and a second output signal after latching the signal, and outputting the output signals to the adder, respectively.

Hereinafter, with reference to the accompanying drawings will be described in detail with respect to the present invention.

FIG. 3 is a block diagram of an ACS unit of a Viterbi decoder according to the present invention. The branch length calculator 100 receives the received data and calculates the length of each branch. ACS which receives the calculated branch length value from the branch length calculating unit 100 and adds the calculated branch length value to the previous path length value, and deletes the long path length value from the two paths that meet each other and selects only the remaining path length value is small. In the general Viterbi decoder including a path storage unit 300 (FIG. 2) storing a maintenance path selected by the ACS unit 200 and the ACS unit 200, the ACS unit 200 includes a first input signal and a first input signal. An adder 210 for receiving two output signals and adding two signals; a first latch unit 220 for latching two addition signals from the adder 210: from the first latch unit 220; Compare selector 230 for comparing two input signals and selecting them: A shift converter for receiving a signal from the compare selector 230 and outputting an output signal according to a control signal CI. (250: Shift Exchange Unit: SEU): Up Third latch unit 260 for latching an input signal from shift converter 250: Multiplexer 270 that selects one signal from each of the two input signals according to control signal C2 and outputs the respective signals And a fourth latch unit for latching signals input from the multiplexer 270 and then outputting a first output signal and a second output signal, and outputting the output signals to the adder 210, respectively. 280).

Here, the adder 210 receives a first input signal and a second output signal from the fourth latch unit 280, and adds the first adder 210-1 to the two signals, and the second input signal. And a second adder 210-2 that receives the first output signal from the fourth latch unit 280 and adds the two output signals.

In addition, the first latch unit 220 receives and latches a first addition signal from the adder 210 and then outputs the first latch 220-1: and the first latch unit 220 from the adder 210. It consists of a second latch 220-2 that receives the two addition signals and latches them.

The multiplexer 270 receives a signal from the shift converter 250 and a first output signal from the fourth latch unit 280 to receive one of two signals according to a control signal C2. The first multiplexer 270-1 to select: and a signal from the third latch unit 260 and a second output signal from the fourth latch unit 280 to receive two signals according to the control signal C2. And a second multiplexer 270-2 for selecting one of the signals.

The fourth latch unit 280 receives and latches a first selection signal from the multiplexer 270 and then outputs a first output signal. The first latch 280-1 and the multiplexer 270. And a second latch 280-2 which receives the second selection signal from the second latch and outputs the second output signal.

4 is a detailed block diagram of the shift converter shown in FIG. 3, wherein the shift converter 250 includes an input signal from the second latch unit 240 (shown in FIG. In response to the signal being received, when the control signal is high, an input signal from the second latch unit 240 (shown in FIG. 3) is output, and when the control signal is low, the first signal outputting the feedback signal of the rear stage fed back. The multiplexer 250-1 and: A latch 250-2 for receiving and latching an output signal from the first multiplexer 250-1 and: The second latch unit 240 is illustrated in FIG. 3. If the control signal is high among the input signal from the input signal from the latch 250-2 and the input signal from the second latch unit 240 (shown in FIG. 3) is output and the control signal is low If is, the second multiple which the input signal from the latch 250-2 is output It consists of the lexer 250-3.

Next, look at the operation and effect of the present invention configured as described above are as follows.

It is necessary to implement a decoder as an application specific integrated circuit (ASIC) for high-speed transmission in HDTV, the most problematic part of the block of the decoder is the ACS part, because the feedback is present in the ACS unit.

The block diagram of the ACS unit of the Viterbi decoder according to the present invention shown in FIG. 3 is designed to minimize the use of the ACS unit. The timing delay generated by reducing the ACS unit can be solved by a pipeline, Timing delay is not a problem because

Referring to FIG. 3 and FIG. 4, the operation will be described. First, a matrix considering the four-state is determined as follows.

The matrix S is a scheduling matrix in which states 0 to 3 are sequentially performed in the ACS unit 200 of FIG. 3.

FIG. 5 is a four-state trellis diagram, where matrix X indicates that there are two paths in the process from each state to the next state as shown in FIG. 5, and as shown in FIG. The first input signal 0 1 2 3 is input to the first adder 210-1 of the adder 210, and the second input signal 0 1 2 3 is input to the second adder 210 of the adder 210. -2) is entered.

The matrix Y is a path metric, as shown in FIG. 3, where the first output signal 2 3 3 3 is input to the second adder 210-2 of the adder 210 and the second output. The signal 0 0 1 1 is input to the first adder 210-1 of the adder 210.

In the first adder 210-1 of the adder 210, a first input signal 0 1 2 3 corresponding to a branch metric and a second output signal 0 corresponding to a path metric 0 1 1) is added, and the result value x is input to the comparison selector 230 through the first latch 220-1 of the first latch unit 220.

In the second adder 210-2 of the adder 210, a second input signal 0 1 2 3 corresponding to a branch metric and a first output signal 2 corresponding to a path metric are included. 2 3 3) is added, and the result value y is input to the comparison selector 230 through the second latch 220-2 of the first latch unit 220.

The comparison selector 230 compares the two input result values (x, y), selects them, and inputs them to the shift converter 250 via the second latch unit 240.

One cycle is performed in four time units, so that the same output is properly output every four time and used as a buffer, multiplexer and shift converter to serve as a path metric input for the next stage.

The first multiplexer 250-1 of the shift converter 250 receives the input signal from the second latch unit 240 and the latch signal of the rear end fed back, and when the control signal C1 is high, the first multiplexer 250-1. When the input signal from the second latch unit 240 is output and the control signal C1 is low, the latch signal of the fed back stage is output. The latch 250-2 of the shift converter 250 outputs the first signal. The output signal from the multiplexer 250-1 is received and latched and then output. The second multiplexer 250-3 of the shift converter 250 outputs an input signal from the second latch unit 240. If the control signal is high among the input signals from the latch 250-2, an input signal from the second latch unit 240 is output, and if the control signal is low, the signal from the latch 250-2 is output. The input signal is output.

The signal output from the shift converter 250 may be directly input to the multiplexer 270 or may be input to the multiplexer 270 via the third latch unit 260.

In the first multiplexer 270-1 of the multiplexer 270, the control signal C2 is high among the input signal from the shift converter 250 and the first output signal from the fourth latch unit 280. In this case, the input signal from the shift converter 250 is selected and output. When the control signal C2 is low, the first output signal from the fourth latch unit 280 that is a feedback signal is selected and output. In the second multiplexer 270-2 of the multiplexer 270, the control signal C2 is output from the input signal from the third latch unit 260 and the second output signal from the fourth latch unit 280. If it is high, the input signal from the third latch unit 260 is selected and outputted. If the control signal C2 is low, the second output signal from the fourth latch unit 280, which is a feedback signal, is selected. To print.

The first latch 280-1 of the fourth latch unit 280 receives and latches the first selection signal from the multiplexer 270, and then outputs a first output signal. The second latch 280-2 receives the second selection signal from the multiplexer 270, latches the second selection signal, and outputs a second output signal.

FIG. 6 is a timing diagram of the ACS calculator shown in FIG. 3, where CLK is a clock signal, x is a first latch 220-1 output signal in the first latch unit 220, and y is a first latch unit 220. ), The second latch 220-2 output signal, z is a value of the shift conversion part 250, 1 is a value of the third latch part 260, and m is a first latch part in the fourth latch part 280. (280-1) value, n is the value of the second latch 280-2 in the fourth latch unit 280, CI is the control signal input to the shift converter 250 and C2 is input to the multiplexer 270 Indicates a control signal.

As described above, according to the present invention, the ACS unit is designed to be implemented as one of the component blocks of the Viterbi decoder in the four-state state, thereby reducing the chip area when implementing the ACS unit as an application specific integrated circuit (ASIC). It can work.

Claims (7)

Branch length calculation unit 100 that receives the received data and calculates the length for each branch, receives the calculated branch length value from the branch length calculation unit 100 and adds to the previous path length value and two at this time A general Viterbi consisting of an ACS unit 200 for deleting a long path length value among the paths of the path and selecting only the remaining path length value and a path storage unit 300 for storing a maintenance path selected by the ACS unit 200. In the decoder, the adder 210 receives the first input signal and the second output signal, adds two signals, and receives the second input signal and the first output signal, and adds the two signals. And: a first latch unit 220 for latching two addition signals from the adder 210; a comparison selector 230 for comparing and selecting two input signals from the first latch unit 220; Comparison selection unit (23 A second latch unit 24 for latching a selection signal from 0): a shift converter 250 for receiving a signal from the second latch unit 24 and outputting an output signal according to a control signal CI: Third latch unit 260 for latching an input signal from shift converter 250: Multiplexer 270 that selects one signal from each of the two input signals according to control signal C2 and outputs the respective signals And a fourth latch unit for latching signals input from the multiplexer 270 and then outputting a first output signal and a second output signal, and outputting the output signals to the adder 210, respectively. Viterbi decoder, characterized in that consisting of. The first adder 210-1 of claim 1, wherein the adder 210 receives a first input signal and a second output signal from the fourth latch unit 280, and adds the two input signals to two signals. And a second adder (210-2) which receives a second input signal and a first output signal from the fourth latch unit (280) and adds the two input signals to the two signals. The first latch 220-1 of claim 1, wherein the first latch unit 220 receives and latches a first addition signal from the adder 210, and then outputs the latched first latch 220-1. And a second latch (220-2) for receiving and latching a second addition signal of the rotor and outputting the latched signal. 2. The second latch unit 240 of claim 1, wherein the shift converter 250 receives the input signal from the second latch unit 240 and the latch signal of the rear end fed back to the second latch unit 240 when the control signal is high. When the input signal is outputted from the control panel and the control signal is low, the first multiplexer 250-1 outputting the feedback latch signal and the output signal from the first multiplexer 250-1 are received. A latch 250-2 output after being latched: and a second latch when a control signal is high among an input signal from the second latch unit 240 and an input signal from the latch 250-2. And a second multiplexer (250-3) outputting the input signal from the latch (250-2) when the input signal from the unit (240) is output and the control signal is low. 2. The signal of claim 1, wherein the multiplexer 270 receives a signal from the shift converter 250 and a first output signal from the fourth latch unit 280, according to a control signal C2. A first multiplexer 270-1 for selecting one of the signals; and a second output signal from the fourth latch unit 280 from the third latch unit 260 according to the control signal C2. A Viterbi decoder comprising a second multiplexer (270-2) for selecting one of two signals. The first latch 280-1 of claim 1, wherein the fourth latch unit 280 receives and latches a first selection signal from the multiplexer 270 and then outputs a first output signal. And a second latch (280-2) configured to receive and latch a second selection signal from the multiplexer (270) and output a second output signal. According to claim 1, wherein the scheduling matrix of the ACS unit 200 Viterbi decoder, characterized in that consisting of the matrix as described above.