JPH01137798A - Time slot changing device - Google Patents

Abstract

PURPOSE:To enable the normal read/write operation of whole address in a temporary memory device to be monitored by providing a monitoring time slot for reading the data of an address for monitoring. CONSTITUTION:Data (dt) receiving the change of the time slot is written in the temporary memory devices 1A and 1B by a write address. At this time, a position where the discrete value of a counter circuit 8 generating the address (Mad) for monitoring and the write address coincide is found, the data corresponding to that position is stored in data holding register circuits 6A and 6B and test patterns (tpa) and (tpb) are inserted to that position of the memory devices 1A and 1B. Next, the time slot for monitoring is provided in course of a read cycle and at the position, the (tpa) and (tpb) corresponding to the (Mad) of the output of the circuit 8 is read from the memory devices 1A and 1B and checked by checking circuits 10A and 10B. Simultaneously to that, the data stored in the register circuits 6A and 6B in course of the write cycle is inserted.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a time slot switching device for switching the time slot positions of a single data string, which is a digital signal, and in particular, to a time slot switching device for switching the time slot positions of a single data string, which is a digital signal. The present invention relates to a double-buffer type time slot switching device that switches time slots using two temporary storage devices.

More particularly, the present invention relates to a function for monitoring normal write and read operations of two temporary storage devices used as double buffers.

[Conventional technology]

Conventionally, a parity check method has been widely used as a means for monitoring temporary storage devices. For example, as shown in FIG. 2, in addition to the valid information data dt, the parity generation circuit 14
1 parity bit is added to the temporary storage device 11.
The temporary storage device 11A sets a rule so that the total number of marks on the write side of A and IIB becomes an odd number or an even number.

Parity check circuits 15A and 15B check whether the number of marks on the read side of the JIB is as specified or not to monitor it.

In FIG. 2, 12A and 12B are selection circuits, respectively, which select the write address W a d or the read address Rad, and select the temporary storage device +1A,
Send to each IIB. The selection circuit 12X selects each output of the temporary storage devices 11A and IIB to store data d.
Output. The write/read control circuit 13 includes a temporary storage device +1A, IIB, and a selection circuit +2A, 12B.
, 12X, as well as parity check circuit! 5A, 15B
control each. Moreover, the parity check circuit 15A,
15B is an error signal ea.

Output eb.

[Problem that the invention seeks to solve]

In the conventional parity checking method described above, one extra bit is required for the parity bit in the temporary storage device, so the capacity of the temporary storage device is required accordingly.

Another drawback is that a failure cannot be detected when the output of the temporary storage device is fixed with the correct number of marks.

An object of the present invention is to provide a time slot switching device that provides a monitoring time slot for reading data at a monitoring address during a read cycle.

[Means for solving problems]

The time slot switching device of the present invention is a device that uses two temporary storage devices to alternately and periodically write and read data to switch the time slot positions of the data. , a means for separately temporarily holding the data at an address location to be monitored while writing the data to the temporary storage device; and a means for temporarily holding the data at an address location to be monitored in the temporary storage device during writing; means for inserting a pattern and during reading of said data from said temporary storage device;
The present invention is characterized by comprising means for inspecting the test pattern read from the monitored address position, and means for transmitting the data temporarily held in +1f increments during the reading.

[For production]

Therefore, according to the present invention, normal read/write operations of all addresses in the temporary storage device can be monitored without interfering with the operation of exchanging time slot positions.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment according to the present invention.
First, to briefly explain the embodiment, two temporary storage devices I perform writing and reading alternately and periodically.
A device that uses time slots A and IB to switch time slots includes a counting circuit 8 that generates an address Mad for monitoring all cells of the temporary storage devices IA and IB, a monitoring address Mad of the counting circuit 8, and A coincidence detection circuit 1 that finds a matching position of the write address W a d, register circuits 6A and 6B that hold data dt at the minus number position, and a test pattern t at that position.
pattern generation circuits 9A and 9B that insert pa and tpb, and a test pattern tpa.

tpb and data dt selection circuits 2A and 2B, and the monitoring address Mad, write address W a d, and read address Rad, which are the outputs of the counting circuit 8.
the selection circuit 2A1.2Bl for switching the monitoring address Mad and the read address W of the counting circuit 8;
A - number configuration circuit 7B that finds matching positions of a and d, and an inspection circuit that checks the pattern at the - number positions!
OA, IOB, and the register circuit 6A at that position.

It has selection circuits 2A2 and 2B2 for inserting the output of 6B.

Further explaining FIG. 1, the first two selection circuits 2A
, 2B respectively select input data dt,
Alternatively, the test patterns tpa and tpb from the two pattern generation circuits 9A and 9B are selected and sent to temporary storage devices IA and IB such as random access memory (RAM).

The second two selection circuits 2A1 and 281 each select the write address W a d, the read address Rad, or the monitoring address Mad from the counting circuit 8, and select the temporary storage device IA.

Send to IB.

10A and IOB are inspection circuits, respectively, which check the patterns from the temporary storage devices IA and IB and output error signals ea and eb in the presence of an error. The register circuits 6A and 6B for holding data each have human data d.
t is temporarily held.

The third two selection circuits 2A2, 282 select the outputs of the temporary storage devices IA, IB, or the outputs of the register circuits 6A, 6B, respectively. The fourth selection circuit 2X selects the outputs of the third two selection circuits 2A2, 282 and outputs data d.

The first coincidence detection circuit 7A detects the write address W a
d and the monitoring address Mad are input, and when a match is detected, the register circuits 6A, 6B and the first selection circuits 2A, 2B are controlled.

The second coincidence detection circuit 7B inputs the read address Rad and the monitoring address Mad, and when a coincidence is detected, controls the write/read control circuit 3.

The control circuit 3 includes register circuits 6A, 6B, temporary storage devices IA, IB, and selection circuits 2A1, 2B1. Pattern inspection circuit 10A, IOB, third selection circuit 2A2
．． 282 and the fourth selection circuit 2X;
control

Next, the operation of the embodiment shown in FIG. 1 will be explained.

First, the data dt whose time slots are replaced is written to the temporary storage devices IA and IB in the write cycle at the write address W a d. At this time, find a position where the count value of the counting circuit 8 (which counts up every cycle to monitor all addresses) that generates the monitoring address Mad matches the value of the write address W a d, and Corresponding data is stored in data holding register circuits 6A and 6B, and a temporary storage device IA.

Test patterns tpa and tpb are inserted into the IB at that position.

In the read cycle, the temporary storage devices IA and IB are read out according to the read address Rad, thereby changing the time slots. However, a time slot for monitoring is provided during the read cycle, and the output of the counting circuit 8 is monitored at that position. test pattern tpa corresponding to address Mad for
tpb is read from the temporary storage devices IA and 1B, checked by the inspection circuits IflA and IOB, and then sent to 7.
The data stored in the register circuits 6A and 6B during the write cycle is inserted. It goes without saying that the above-mentioned processing can be performed for all addresses that can be checked for writing/reading in the two temporary storage devices IA and IB.

(Effects of the Invention) As described above, in monitoring a temporary storage device used in the double buffer method, the present invention stores data at an address to be monitored during writing in a register, and also stores a test pattern at that location. By inserting the above test pattern and checking the above test pattern at the monitoring time slot position during the read cycle, and inserting the above data stored in the register during the write cycle, it is possible to prevent the time slot switching operation from occurring. This has the advantage that normal read/write operations of all addresses in the temporary storage device can be monitored without having to read or write data.

[Brief explanation of the drawing]

It is. l A, I B ----- Temporary storage device, 2
A, 2B, 2A1.2B1.2A2.2B22x...
...Selection circuit, 3------------------- Write/read control circuit, 6A, 6B--Register circuit, 7A, 7B... ...-Number structure circuit, 8
・・・・・・・・・・・・・・・Counting circuit, 9A
, 9B------Pattern generation circuit, 10A, IGB
--------Pattern inspection circuit.

Claims (1)

[Scope of Claims] 1) In an apparatus that uses two temporary storage devices, writes and reads data alternately and synchronously, and replaces the time slot position of the data, at least Means for separately temporarily holding the data at a monitored address position while writing the data to the storage device, and inserting a test pattern into the monitored address position of the temporary storage device during the writing. means for inspecting the test pattern read from the monitored address location during reading of the data from the temporary storage device; and means for inspecting the test pattern read from the monitored address location while reading the data from the temporary storage device; A time slot switching device characterized by comprising: means for sending. 2) The means for temporarily holding the data is a register circuit, the means for inserting the test pattern is a selection circuit and a first coincidence detection circuit, and the means for inspecting the test pattern is a register circuit. 2. The time slot switching device according to claim 1, wherein the checking circuit and the means for transmitting the temporarily held data are a control circuit and a second coincidence detection circuit.