JPH0254357A - Temporary memory circuit - Google Patents

Abstract

PURPOSE:To realize the replacement of slots for valid data in terms of time by setting a monitor time slot at an address in a temporary memory circuit to monitor the cell corresponding to the address and fixing the time slot at a fault address when the cell has a trouble. CONSTITUTION:A collation circuit 6 collates the count output of a test address counter 5 with a read address and inputs the result of this collation to a selection circuit 8. A selection circuit control signal producing circuit 14 selects the read address or an address +1 and supplies it to the selection circuits 9A and 9B respectively. Then the main signals are read out of the temporary memory circuits 10A and 10B based on the outputs given from both circuits 9A and 9B and the control output of a read/write control circuit 12. The test signals are read out and collated with each other by a test signal collation circuit 11. The errors, if occurred in the circuits 11A and 11B, are sent to the circuit 14. The circuit 14 produces the control information to be sent to both circuits 2 and 8. Then a monitor time slot is fixed at a fault address.

Description

Detailed Description of the Invention (Industrial Field of Application) The present invention relates to a temporary memory circuit, and in particular to two temporary memory circuits used as double buffers in a double buffer method, which is one method for exchanging time slots of digital signals. The present invention relates to a temporary storage circuit that is characterized by detection and switching of faulty cells.

(Prior Art) Conventionally, a parity check method has been widely used as a method for monitoring negative time memory circuits. This method adds one parity bit to the valid information, and sets a rule so that the total number of marks on the write side is an odd or even number.On the other hand, on the read side, the number of read marks is Monitoring is carried out by checking whether the rules are being followed. Through this check, if a parity check error is detected, the current temporary storage circuit is switched to a pre-prepared backup temporary storage circuit.

(Problems to be Solved by the Invention) In the conventional temporary storage circuit described above, although an error in the -time storage circuit can be detected, it is not possible to specify a faulty cell in the storage circuit. Therefore, there is a drawback that if even one cell fails, the failed temporary storage circuit becomes unusable.

(Means for Solving the Problems) The temporary storage circuit according to the present invention is a temporary storage circuit consisting of two pieces that alternately and periodically performs writing and reading, and exchanges time slots, and the temporary storage circuit is a temporary storage circuit that performs writing and reading in an alternating and periodic manner and replaces time slots. an insertion means for setting a monitoring time slot and inserting a test signal; an address counter for generating write and read address signals for the test signal; and a comparison means for comparing the address counter and the read address of the data signal. , a first selection means for outputting the read address and a value obtained by adding 1 to the read address in accordance with a comparison result of the comparison means; and a first selection means for outputting the data signal address and the test signal address by switching between the data signal address and the test signal address. 2 selection means, a collation means for detecting an error in the read test signal, and a selection circuit for creating a control signal to the insertion means and the first selection means based on the error output from the collation means. and control signal generating means.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention. As shown in FIG. 2, the time slot switching device operates by writing data D1 to D14 in the order according to addresses 1 to 14. In order to switch time slots, the read addresses 13, 10, 3, 1, . 5...
When the address is changed as shown in FIG. DI, D5... are read out. The result + (Di, D2.D3.D4.D
5...)-(DI3.DIO, D3.Di, D5...
・) This means that the time slots have been replaced in terms of time.

Referring to FIG. 1 and FIG. 3, first, the data input for time slot swapping includes a delay circuit 1 and a selection circuit 2.
A monitoring time slot is created at an arbitrary position.

This is because the output of the 0 selection circuit 2 and the output of the test signal generation circuit 3 shown by the hatched area of the RAM data input in FIG. 3 are input to the selection circuit 4, and the test signal is inserted into the data input. The signal into which this test signal has been inserted is written to the corresponding write address shown in FIG. 3 in the temporary storage circuits 10A and 10B, which are constituted by, for example, RAM. At the time of reading, reading is performed using a random address as shown in FIG.

The read data output is shown in FIG.

However, in period n, the number of writes to addresses 6 and above is increased by 1 due to the insertion of monitoring time slots. In FIG. 1, the read address is the matching circuit 6. Addition circuit 7
- supplied to the selection circuit 8; The adder circuit 7 adds 1 to the input read address and sends it to the selection diagram #18. The collation circuit 6 collates the count output of the test address counter 5 and the read address, and inputs the collation result to the selection circuit 8. The 0 selection circuit 8 operates under the control of the selection circuit control signal generation circuit 14 according to the collation result. Which of the read address and read address 11 is selected and supplied to selection circuits 9A and 9B. In the selection circuits 9A and 9B,
The address from the test address counter 5 and the write address are supplied. In this way, selection circuit 9A
, 9B and the read/write control circuit 12
Based on the control, the main signal is read out from the - time storage circuit 10A and IOB, and then the test signal is read out and checked by the test signal checking circuit 11.

In the next cycle n+1, the next address check is performed by shifting the monitoring time slot by one. If an error occurs from the test signal matching circuits 11A and IIB,
The error information is sent to the selection circuit txJ signal creation circuit 14, which creates control information to be sent to the selection circuit 2 and the selection circuit 8, and fixes the monitoring time slot to the faulty cell address. - The signals read from the time memory circuit 10A and IOB are outputted as data output via the selection circuit 13.

(Effects of the Invention) As explained above, the present invention monitors a cell corresponding to an address by setting a monitoring time slot to an address in a temporary storage circuit, and if the cell is out of order, By fixing the monitoring time slot to the address of the faulty cell, the effective data time slot can be replaced in time even if a cell in the -time storage circuit fails.

Sawa circuit, 3...Test signal generation circuit, 5...Test address counter, 6...Verification circuit, 7...Addition circuit, 10A, IOB...-hour storage circuit, 11...
Test signal verification circuit, 12... Read/write control circuit, 14... Selection circuit control signal generation circuit.

Claims (1)

[Claims] A temporary storage circuit consisting of two circuits that alternately and periodically performs writing and reading and exchanges time slots, and an insertion means that sets a monitoring time slot at an arbitrary position of a data signal and inserts a test signal. an address counter for generating write and read address signals for the test signal; a comparing means for comparing the address counter and the read address of the data signal; a first selection means for outputting a value obtained by adding 1 to the address; a second selection means for switching and outputting the address for the data signal and the address for the test signal; A temporary storage circuit comprising: collation means for detection; and selection circuit control signal generation means for generating control signals to the insertion means and the first selection means based on error output from the collation means.