JPH06139086A - Error detecting device and error detecting method - Google Patents

Abstract

PURPOSE:To detect the error of bank data with relatively small hardware amount even though the address space of a memory is wide by providing a parity bit for each bit string of bank data with an arbitrary size. CONSTITUTION:For example, a memory has 128 addresses and is provided on every 8 bank data corresponding to 8 addresses following the parity bit. When a readout request comes, bank data showing the memory which holds the readout data is taken out from a bank 2. At the same time, the bit string between the parity bit (READ parity) related to the READ bank data and the bank data related to the READ parity is taken out. The error of the bank data can be detected by performing the parity check for the bit string of the READ parity and bank data read out by a parity check circuit 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error detecting method in a circuit capable of simultaneously performing an output operation and an input operation. A data transfer control circuit, in particular, a circuit that controls data transfer between a channel and a main memory, temporarily stores data in a semiconductor memory, and then waits for the timing to transfer the data to the channel or main memory. is necessary.

At this time, a data write request and a data read request may occur simultaneously to the data transfer control circuit. However, the semiconductor memory cannot take the write operation while the read operation is being performed.

Therefore, in general, two semiconductor memories equivalent to the control circuit are prepared so that when a write request is made while data is being read by one memory, data is written to the other memory. ing. With this configuration, the data transfer control circuit can process the read request and the write request at the same time.

In such a control circuit, when reading data from a semiconductor memory, it is necessary to determine from which memory the data should be read. For that purpose, we have flip-flops for each address,
In this flip-flop, the memory in which the data is written is recorded.

When reading data, the address control circuit determines the memory holding the read data by referring to the content of the flip-flop corresponding to the address. At this time, if there is an error in the value of the flip-flop, completely different data is read out, which seriously affects the system. Therefore, it is necessary to detect an error in the flip-flop.

[0006]

2. Description of the Related Art FIG. 2 is a diagram showing an outline of a control circuit for data transfer. To make a read request to this control circuit, turn on the READ valid signal,
Specify the READ address. At the same time, from the flip-flop corresponding to the READ address, there are two memories 2
The bank data indicating which of 0 and 21 holds the read data is read.

The address control circuit 22 turns on the READ valid signal to the [memory 0] 20 when the bank data points to the [memory 0] 20. At this time, the READ valid signal to the [Memory 1] 21 is
It is off because it is the inverted READ valid signal to [Memory 0] 20.

After turning on the READ valid signal to the [memory 0] 20, the address control circuit 22 specifies the READ address for the [memory 0] 20. In this way, the correct data held at the READ address is read from the [memory 0] 20.

On the other hand, when a write request is made during this read operation, the WRITE valid signal is turned on to specify the WRITE address. At the same time, WRI
Write new bank data to the flip-flop corresponding to the TE address. This bank data points to the memory in which the read operation is not performed, that is, [Memory 1] 21.

The address control circuit 22 uses the [memory 0] 2
Since the read operation is being performed at 0, the WRITE valid signal to [Memory 1] 21 is turned on. At this time, the WRITE valid signal to the [Memory 0] 20 is an inversion of the WRITE valid signal to the [Memory 1] 21, and is therefore off.

After turning on the WRITE valid signal to the [memory 1] 21, the address control circuit 22 specifies the WRITE address for the [memory 1] 21. In this way, data is written to the specified WRITE address.

FIG. 3 is a diagram showing a bank. Bank 3
Reference numeral 1 is usually composed of a flip-flop and stores bank data. Flip-flops are provided as many as the number of addresses corresponding to the addresses of two equivalent semiconductor memories, so the READ address or WR
If the ITE address is designated, the flip-flop corresponding to the address can be selected.

As described above, when a write request is issued while one semiconductor memory is performing a read operation, it is necessary to update the value of the corresponding flip-flop. The new value of the flip-flop is, of course, RE which points to the memory in which the read operation is taking place.
The AD bank data is inverted.

By the way, the values of the flip-flops forming the bank may be erroneous for some reason. In this case, the RE received by the address control circuit 30
Since the AD bank data points to the memory in which the read data is not held, completely different data is read.

In order to detect such a serious error, one set of banks has conventionally been added, and two sets in total have been prepared.
Then, the READ bank data output from each bank is checked for the same value to detect an error.

[0016]

FIG. 4 is a diagram showing a conventional error detecting device having two sets of banks. In FIG. 4, the bank 40 and the bank 41 are assumed to be composed of flip-flops that store the same bank data. The EOR circuit 42 outputs the READ bank data output from the bank 40 and the R output from the bank 41.
By inputting EAD bank data, it is detected whether or not both values are equal.

The EOR circuit 42 turns off the bank error signal when both READ bank data values are equal, and turns on the bank error signal when both READ bank data values are different. Therefore, the output of the bank error signal makes it possible to detect an abnormality occurring in the flip-flop of either bank 40 or 41.

However, for example, two sets of equivalent memories each have a capacity of 128 × 8 bytes, and the addresses are # 0 to #.
In the case of 127, one bank consists of 128 flip-flops. Therefore, if two sets of banks are provided for error detection as in the conventional case, a total of 256 flip-flops must be provided.

As described above, in the conventional error detecting method,
When the semiconductor memory has a large address space and a large number of flip-flops are required to form a bank, the amount of hardware for detecting a bank error becomes huge.

The present invention has been made in view of such conventional problems. Even if the address space of the semiconductor memory is large, the amount of hardware is relatively small and the entire control circuit is large. It is an object of the present invention to provide an apparatus and method for detecting an error in bank data without making a large-scale modification to the structure.

[0021]

According to the invention, the above mentioned objects are achieved by the means recited in the patent claims.

That is, the invention of claim 1 is provided with two sets of memories having the same address so that the output operation and the input operation can be performed at the same time, and which of the two equivalent memories has the input data. In a storage device having a bank for storing bank data indicating whether or not data has been written, the entire address of the memory is divided into a plurality of groups including some addresses, and a parity bit is set for each group. Is a means for storing a parity check, a means for performing a parity check, and a means for updating a corresponding parity bit when the bank data is changed.

The invention of claim 2 is the bank data corresponding to the write address designated for writing the data when writing the data to either of the two sets of memories, and is already stored in the bank. In the error detecting device, which compares the stored data with the bank data indicating the memory to which the data is to be written, and if the two are different, the means for changing the parity bit of the set to which the write address belongs is provided. is there.

According to a third aspect of the present invention, when the data written in any one of the two sets of memories is read using the error detecting device according to the first aspect, the written data is read. For the group to which the read address specified in, belongs, the bank data corresponding to all addresses included in the group and the parity bit of the group are read, and a parity check is performed to detect an error in the bank data. Is the way.

[0025]

According to the present invention, in order to detect an error in bank data, a parity bit is provided for each bit string of bank data having an arbitrary fixed size. Then, the parity check may be executed only on the bit string including the bank data corresponding to the address of the read data.

Therefore, for example, if the memory has a capacity of 128 × 8 bytes, has 128 addresses, and parity bits are provided for every 8 bank data, the number of flip-flops added for error detection is , 16 (128 ÷ 8 = 16).

When the flip-flops holding the bank data are combined, the total number of flip-flops required in the present invention is 144 (128 + 16 = 144). Conventionally, as many as 256 flip-flops have been required, so the amount of hardware for error detection is greatly reduced.

[0028]

FIG. 1 shows an embodiment of the present invention. here,
The memory has 128 addresses, and the parity bit is provided for every 8 bank data corresponding to 8 consecutive addresses. In this case, WRI
The TE address and the READ address can be composed of seven bits, but a parity address can be generated by using four bits excluding the lower three bits.

In FIG. 1, when there is a read request, bank data (hereinafter, referred to as "READ bank data") indicating the memory holding the read data is fetched from the bank 2 by the designated READ address. At the same time, a parity bit related to this READ bank data (hereinafter referred to as "READ parity").
And a bit string of bank data relating to this READ parity.

According to the read READ bank data,
The address control circuit 1 can select the memory holding the read data. In addition, the parity check circuit 3 detects that the bank data error in question is
It can be detected by performing a parity check on the read READ parity and the bit string of the bank data.

Further, when a write request is issued during this read operation, the bank data (hereinafter, referred to as the bank data) corresponding to the WRITE address is read as in the case of the READ address.
It is called "WRITE bank data". ) Take out. At the same time, a parity bit related to this WRITE bank data (hereinafter referred to as "WRITE parity") is taken out. It is not necessary to take out the bit string.

The parity changing circuit 4 uses the read WRI.
The TE bank data is compared with the bank data to be newly stored in the bank (inversion of the READ bank data), and if the values do not match, the WRITE parity value is inverted and a new parity bit is set. Save as.

[0033]

As described above, according to the present invention,
In the data transfer control circuit, it is possible to detect an error in the bank data output by the bank configured by the flip-flops provided to control the memory switching with a configuration in which the amount of hardware is significantly reduced compared to the conventional configuration. There is an advantage. The present invention is particularly effective when the bank capacity is large.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing an outline of a control circuit for data transfer.

FIG. 3 is a diagram showing a bank.

FIG. 4 is a diagram showing a conventional error detection device provided with two sets of banks.

[Explanation of symbols]

 1, 22, 30 Address control circuit 2, 31, 40, 41 Bank 3 Parity check circuit 4 Parity change circuit 20, 21 Memory 42 EOR circuit

Claims (3)

[Claims] 1. A set of two memories having the same address so that an output operation and an input operation can be performed at the same time, and bank data indicating to which of the two equivalent memories the input data is written. A storage device having a bank for storing, and a means for storing the parity bit to be set for each set by dividing the entire address of the memory into a plurality of sets including some addresses; An error detecting device comprising means for checking and means for updating a corresponding parity bit when the bank data is changed. 2. Bank data corresponding to a write address designated for writing data when writing data to either of the two sets of memories, which is already stored in the bank. 2. The error detection device according to claim 1, further comprising means for comparing bank data indicating a memory for writing data and changing the parity bit of the set to which the write address belongs when the two are different. 3. When the data written in any one of the two sets of memories is read using the error detection device according to claim 1, a read address designated for reading the written data belongs. An error detection method, wherein each bank data corresponding to all the addresses included in the set and the parity bit of the set are read out and a parity check is performed to detect an error in the bank data.