JPH01136366A - High breakdown-strength semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To thin a metallic wiring, and to flatten an element surface by making an insulating film of a multilayer and forming a stepped section into a plurality of steps in a field plate structure and reducing stepped quantity per one step. CONSTITUTION:A P-type impurity diffusion layer 12 and a hot SiO2 film 13 while covering a junction section on the main surface of the P-N junction are formed on the main surface of an N-type single crystal Si substrate 11. A stepped section A is shaped by a CVD-SiO2 film 14 formed onto the hot SiO2 film 13 while being slightly separated from the upper section of the P-N junction section. A stopped section B is shaped onto the SiO2 film 14 and near the stepped section A by an intermediate insulating film 15 used for multilayer interconnections, etc. A metallic wiring 16 from an exposed section, from which the hot SiO2 film 13 is bored, in the P-type impurity diffusion layer 12 passes on the hot SiO2 film 13 and coats the stepped section A, passes on the SiO2 film 14 and coats the stepped section B, and is led out onto the intermediate insulating film 13, thus organizing MOS structure. That is, since a stepped section corresponding to a conventional one stepped section is composed of two steps of A and B, stepped quantity is reduced, and flattened. Accordingly, even when film thickness is thinned in the metallic wiring 16, the wiring 16 is not disconnected at the stepped section A and said stepped section B.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device, and particularly to a high voltage semiconductor device having a field-great structure and a method for manufacturing the same.

(Prior art) Conventional high-voltage semiconductor devices include, for example, the literature:
, J, A, P, vol 23. F&i4. April
il 1984 PP, 415-419 “5tru
ctual analysis and experiment
mental characteristic of H
lgh Voltage Bipolar Trans
istors with ahallw junction
nJ) et al.

FIG. 3 is a sectional view showing a typical structure of a conventional high voltage semiconductor device.

In FIG. 3(a), on the main surface side of the N-single-crystal St substrate 1, there is a P middle layer 2 that will become an anode and the N″″ single-crystal 8.
An N+ diffusion layer 3 serving as a so-called cand for taking out electrodes from one substrate 1 is formed. The metal wiring 4 from the P+ diffusion layer 2 is coated with a thermal stow film 5, CVD to alleviate electric field concentration near the bonding surface when a high reverse bias is applied.
It has a so-called field-grate structure in which the single crystal 81 is extended over the substrate 1 through the film 6. This configuration achieves high voltage resistance. In this field-great structure, the places where the electric field strength tends to increase are the junctions f''&
, 81 (% step part 7 Shimojima.

Three locations are considered: E, below the field shoulder, and in order to obtain a high breakdown voltage, it is necessary to lower the maximum electric field strength at E+ and Et-Es as much as possible.

In general, the electric field strength of
and the thickness of the Sin film under the wiring metal 4 (toxx,
toxx) etc. In the figure, the broken line is the boundary of the depletion layer formed by the electric field.

S1 under 9 metal wiring 4 determined by withstand voltage simulation
0. Film thickness to! 1, E for t(131'!
, E, , E, The maximum electric field dependence at the section is, for example, as described in the above-mentioned literature, in order to lower the maximum electric field value at each section, %E, sio at the section, film thickness tO! 1 is made thinner, the step amount of the 5ift film is made smaller in the edge part, and SiO! is made thinner in the 81st part. #Tox needs to be strengthened. The heat S10. The thickness of the membrane 5 is made as thin as possible, and the thickness of the CVD-8i pseudo membrane 6 is made as thick as possible. For example, P+ diffusion layer 2 as an anode
To achieve a junction breakdown voltage of 400 V or more with a junction depth of 5 Jm or less, toxlC thermal SkO@film 5 thickness] should be 0.5 to 0.
8 μm.

toflC thermal stow film 5 thickness + CVD-8iO, film 6 thickness] was set to 2.0 to 2.5 μm.

(Problem to be Solved by the Invention) However, in the device with the above configuration, in order to make the device high withstand voltage, steps are provided in the SiOg film as an intermediate insulation and edge film to reduce the maximum electric field value under the field grade electrode. However, the flatness of the surface is significantly impaired due to the large step difference caused by the Sin and film, and as a result, the metal wiring installed on the step part is prone to step breakage, and conversely, the step breakage has to be taken into account. TeSt
If the amount of step difference in the O, film is reduced, the maximum electric field value increases due to the decrease in the StO film thickness, and electric field concentration occurs, resulting in a decrease in breakdown voltage. af, there is a problem in that if the film is made thicker than necessary, the levelness of the wall is impaired, which hinders multilayer wiring.

The present invention eliminates the above-mentioned problem of breakage of metal wiring due to the difference in film level and loss of flatness of the element surface, and improves the flatness of the element surface without causing a decrease in element breakdown voltage. An object of the present invention is to provide a semiconductor device having an element structure suitable for a high voltage IC, and a method for manufacturing the same.

(Means for Solving the Problems) A high voltage semiconductor device according to the present invention is a semiconductor device with a field grade structure, in which an insulating film on which an electrode is formed is multilayered to form a plurality of steps. be.

A method for manufacturing a high voltage semiconductor device according to the present invention is a method for manufacturing a semiconductor device having a field grade structure, in which a second insulating film is formed at a desired position on an i-th insulating film on a semiconductor substrate, and a first A step is formed, a first wiring electrode is provided to cover the first step, a third insulating film is formed on the second insulating film, and an end portion of the first wiring electrode is formed. A second step is formed by removing a portion near and above the step, and a second wiring electrode is provided which is connected to the first wiring electrode and covers the second step.

(Function) The high voltage semiconductor device and the manufacturing method thereof according to the present invention include:
By creating a field-grade structure with multiple steps in the insulating film under the wiring electrode and reducing the amount of steps per step, the wiring electrode, which is a field-grade electrode, can be made thinner, making it possible to flatten the element surface. Moreover, the voltage resistance can be increased higher than that of the conventional structure.

(Example) Hereinafter, an example of the present invention will be described in detail based on the drawings. FIG. 1 is a cross-sectional view of a main part of a semiconductor device according to an embodiment of the present invention, particularly showing an improved part of the conventional semiconductor device shown in FIG. 3, with other parts omitted. In the same figure, a P-type impurity diffusion layer 12 is formed on the main surface side of an N-type single crystal 81 substrate 11, and a thermal Sin film 1 is applied to cover the bonding portion of the PN junction that is exposed on the main surface.
3 is formed. Also, heat S10. ! II: l: formed tail CVD-
8IO.

A stepped portion A is formed in the membrane 14. Furthermore, C.C.
A stepped portion B is formed near the stepped portion A by an intermediate insulating film 15 formed on the VD-8to film 14 and used for multilayer wiring, etc. The metal wiring 16 is transferred from the exposed part of the P-type impurity diffusion layer 12 where the film 13 is opened to the heat S1 to the film 1
3 to cover the stepped part A, and further cover the CVD-Si
The intermediate insulating film 1 is completely passed over the Ot film 14 and covers the stepped leather part B.
5, forming an MO8 structure. That is, in this embodiment, since the conventional one-step step is composed of two steps, the step portion and the step B, each step portion A
, H are made sufficiently smaller than conventional ones (for example, from 2 to 2.5 μm in the conventional case to 0.8 μm in this example), and are flattened. Therefore, the thickness of the metal wiring 16i becomes thinner (
For example, even if the thickness is 0.1 μm), there will be no breakage at the stepped portions A and B.

If the P medium-sized impurity diffusion layer 12 is made into a negative pipe through the intermetal a16, the depletion layer formed around the P-type impurity diffusion layer 12 becomes shallow in a stepwise manner at the stepped portions A and B. ,
The thickness of the oxide film directly under the lead-out end of the metal wiring 16 has a large effect on the withstand voltage, but there is heat 5L at the two steps A and B.
The thickness of the intermediate insulating film 15 is determined to be a sufficient thickness between the thickness of the OT film 13 and the thickness of the CVD-8ift film 14 . Therefore, this semiconductor device has high voltage resistance.

Next, a method for manufacturing a high voltage semiconductor device will be explained with reference to the process diagram of FIG.

First, in FIG. 2(a), after forming an insulating film 22 such as a thermal SlO film on the main surface side of a Nm single-crystal St substrate 21, the insulating film 22 is partially etched by normal photo-etching. An opening is opened, and impurities in the P disk are diffused through the opening to form a pace diffusion region 23.

Next, as shown in FIG. 2(b) K, after removing the insulating film 22, an insulating film 24 such as a thermal 8101 film having a thickness of 500λ is again formed on the main surface side of the single crystal 81 substrate 21 as a first insulating film. The insulating film 24 is then formed by normal photoetching.
is partially opened to partially expose the surface of the pace diffusion region 23, and also partially expose the surface of the single crystal St substrate 21 spaced a predetermined distance from the pace diffusion region 23. Diffuse the impurities through these openings and fill the diffusion area 2.
3, a two-pick diffusion region 25 and a collector diffusion region 26 are formed.

Next, as shown in FIG. 2(c), a second insulating film (CVN) is deposited on the insulating film 24 using a chemical vapor deposition method (CCVD method).
-sto, a film 27 is formed, and then F) CVD-810, I [27 is turned by a normal photolithography process to form a stepped portion A at a desired position on the field. This stepped portion A is located between the pace diffusion region 23 and the single crystal S.
It is formed at a position above the single-crystal St substrate 21 and a little away from the junction with the T-substrate 21 . In addition, cvD-st
o! The film thickness of the film 27 is determined by taking into account the capacitance at the stepped portion A of the first layer metal wiring 28. ooAヮTyosu.

Next, as shown in FIG. 2(d), after forming contact holes on the base diffusion region 23, emitter diffusion region 25, and collector diffusion region 26 by a photolithography process, the insulating film 24 and the CVN-SIO , a first wiring metal is deposited on the entire surface of the main surface of the substrate on the film 27, and then turned to form a first metal wiring 28t as a first wiring electrode.
- form. At this time, the first metal gap 82B is set to, for example, 10,000λ or less in consideration of the flatness of the element surface.

The field grade electrode in contact with the base diffusion region 23 in the first metal wiring 28 is a C V D -S i Ox that just covers the stepped portion A from above the insulating film 24 .
It is formed up to the membrane 27 portion.

Next, as shown in FIG. 2(e) K, an intermediate insulating film 29t-CVD is formed as a third insulating film in order to insulate between wiring metals.
Generates over the entire surface by law. At this time, the thickness of the intermediate insulating film 29 is set to, for example, s, ooo to 10.000λ so as to obtain a sufficient breakdown voltage between wirings (for example, 400V or more).
・Then, the first metal wiring 28 for taking out the base electrode
A portion of the intermediate insulating film 29 is removed by photoetching from the end of the field grade electrode to the vicinity thereof to form an opening. As a result, a stepped portion B is formed near the stepped portion A.

Next, as shown in FIG. 2(f), a second wiring metal is deposited on the entire surface of the intermediate insulating film 29 and patterned to form the first wiring as an extension of the field grade electrode end.
forming a second metal wiring 30 connected to the metal wiring;
The second metal wiring 30t serving as the second wiring electrode is connected to the field grade electrode end of the first metal wiring 28 for taking out the base electrode, and covers the stepped portion B to cover the intermediate insulating film 29 near it. to be located. Thereafter, a passivation film 31f is formed on the entire surface, thereby completing a high breakdown voltage NPN transistor according to the present invention.

In the above description, a field grade structure having a step in the sio film has been described, but it is also effective as a countermeasure against step breaks in ordinary field grade metal wiring without a step.

Furthermore, in this embodiment, an NPN type transistor element is taken as an example, but the present invention can also be applied to any other high voltage semiconductor device having a finild-grate structure, and the same effect as in the above embodiment can be obtained. play.

(Effects of the Invention) As described above in detail, according to the present invention, the insulating film is multilayered in the field grade structure to have multiple steps, and the amount of each step is reduced. The metal wiring, which had been made thick to improve the stepping force at stepped portions, can now be made thinner, making it possible to flatten the surface of the element.

In addition, since the step t at the bottom of one step is small and the film thickness under the edge of the field-grade metal wiring can be increased by using an intermediate insulating film, the electric field strength directly under the step and the field-grade edge can be reduced. It is expected that the voltage resistance will be higher than that of semiconductor devices with conventional structures. In other words, when obtaining the same breakdown voltage as the conventional one, the field grade length can be made shorter than the conventional one, so it is expected that the element size will be reduced.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of essential parts of a high-voltage semiconductor device according to an embodiment of the present invention, FIG. 2 is a process diagram of a high-voltage semiconductor device according to an embodiment of the present invention, and FIG. 3 is a cross-sectional view of a conventional device. be. In the figure, 11...N-type single crystal 81 substrate, 12...P base impurity diffusion layer, 13...thermal SiO, film, 14...
・CVD-St O! Film, 15... Intermediate insulating film, 1
6... Metal wiring, 21... Single crystal 81 substrate, 22...
... Insulating film, 23... Base diffusion region, 24... Insulating film, 25... Emitter diffusion region, 26... Collector diffusion region, 27... CVD-8lO* film, 28...
- First metal wiring, 29... intermediate insulating film, 30...
2nd gold IR arrangement, 3T... armpitation film, A, B... step portion. 0 Shiko
li\--1'-

Claims (2)

[Claims] (1) In a high voltage semiconductor device with a field grade structure in which an electrode connected to a diffusion layer formed on the surface of a semiconductor substrate is wired on an insulating film formed on the semiconductor substrate, the above insulating film is multilayered. A high-voltage semiconductor device characterized by having multiple steps. (2) A first step of forming a first insulating film on the main surface side of the semiconductor substrate on which the diffusion layer is formed, and forming a second insulating film at a desired position on the first insulating film. a second step of forming a first step at a position away from above the diffusion layer; and a third step of forming a first wiring electrode that contacts the diffusion layer and covers the first step. a fourth step of forming a third insulating film on the first wiring electrode and the second insulating film; a third insulating film near the end of the first wiring electrode on the second insulating film; a fifth step of removing an insulating film portion to form a second step; and a sixth step of forming a second wiring electrode connected to the first wiring electrode and covering the second step. A method for manufacturing a high voltage semiconductor device.