JPH01293660A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To satisfactorily match a transistor characteristic by a method wherein a first opening part of a base and a first opening part of a collector are formed individually on first separate metal wiring parts, they are connected by second metal wiring parts and individual electrodes of a transistor are constituted separately. CONSTITUTION:Base regions 25 are formed in island regions, then, emitter regions 26 and collector-electrode extraction regions 27 are formed. Then, insulating films 28 are formed; one part of the insulating films 28 on the island regions is removed; first opening parts 29 are formed. Then, first metal wiring parts 30 are formed so as to cover the first opening parts 29. Then, one part of a plasma nitride film of an interlayer film formed on the whole surface is removed selectively; second opening parts 33 are formed. Then, the second opening parts 33 on the first metal wiring parts 30 which are connected to the two or more emitter regions 26, the two or more base regions 25 and the two or more collector-electrode extraction regions 27 are connected individually by second metal wiring parts 32; individual emitter, base and collector electrodes are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having a multi-emitter structure and multilayer wiring.

[Conventional technology]

In recent years, mass production of multilayer wiring has become possible by using a plasma nitride film as an interlayer film in linear circuit semiconductor devices for power supplies of about 10 to 50 V. In a typical linear circuit, the driver transistor in the output stage requires several tens of mA.
A design has been made that allows collector current to flow. When the driving transistor is an NPN (NPN) transistor, the emitter The structure is such that the region is divided into a plurality of regions and base contacts are provided between them.

Figures 4(a) and 4(b) show conventional NPs with multiple emitter structures.
FIG. 2 is a plan view and a sectional view taken along line cc' of an example of an N transistor.

An N+ type buried region 2 is provided on a P type semiconductor substrate 1,
An N-type epitaxial layer 3 is formed on the main plane with a resistivity of several Ω·l and a thickness of several μm to several tens of μm.Next, a P-type insulating isolation region 4 is formed by a photolithography process. After the process, P type base region 5, N+
A type emitter region 6 and an N+ type collector electrode extraction region 7 are provided by performing a diffusion and oxidation process, and an insulating film 8 is also provided at the same time.

Next, the insulating film 8 in each region is removed to provide a first opening 9 for taking out the electrode.Next, a first metal wiring 10 is sputtered or vapor deposited using aluminum or the like and subjected to a photolithography process. establish. At this time, each emitter region 6 is connected by a first metal wiring 10, each base region 5 is also connected by a first metal wiring 10, and each collector electrode extraction region 7
are connected by the first metal wiring 10 and then an interlayer is provided on the entire surface using a plasma nitride film or the like, and then a second opening 13 is formed between the respective electrodes in order to connect the first metal wiring 10 and the second metal wiring 12. An emitter electrode, a base electrode, and a collector electrode are formed by providing and connecting to the electrodes.

[Problem to be solved by the invention]

In the above-described conventional NPN transistor having a multiple emitter structure, each N+ type emitter region 6 is connected to the first metal wiring 10.
, each P type base region 5 and each N+ type collector electrode extraction region 7 are connected to each other, and a second metal wiring 12 is provided after a second opening 13 of an interlayer through hole is provided therein. . Therefore, there are the following drawbacks6.
First, in an NPN transistor with a multiple emitter structure, the emitter and collector currents flow on the order of several tens of milliamps, so from the relationship between electromigration and current density, the first
As a result of the need to thicken the metal wiring 10 as necessary,
This increases the area occupied by the element.

Second, as shown in FIG. 2(a), the first metal
Since all contacts of the base electrode are connected at
It is necessary to provide the first metal wiring 10 between the N-type collector electrode extraction region 7 and the P-type base region 5. This requires increasing the collector area, leading to an increase in the capacitance between the collector area and the ground area, which leads to deterioration of the frequency characteristics of the transistor. For example, when calculating a ratio of 1:2, it is necessary to change the collector area ratio to 1:2 as well, and a transistor with a ratio of 1 also requires an extra collector area. This leads to an increase in parasitic capacitance, which is a drawback in terms of frequency characteristics.

[Means to solve the problem]

The semiconductor integrated circuit of the present invention has a plurality of emitter regions, one or more base regions, and one or more collector regions in one island region insulated and isolated on one main plane of a semiconductor substrate. An insulating film is provided on the main plane, a plurality of first openings are provided in the insulating film in each region, a first wiring layer is provided in each of the plurality of first openings, and an interlayer including a layer on the first wiring layer is provided. an insulating film is provided, a second opening is provided in the interlayer insulating film, and the plurality of emitter regions, the one or more base regions, and the one or more collector regions are respectively connected separately. The structure includes a transistor provided with a second wiring layer.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1(a) and 1(b) are a plan view and a sectional view taken along the line AA' of a first embodiment of the present invention.

Impurity concentration is IQ 15~1Q 17/Cal
An N+ type buried region 22 with a sheet resistance of several tens of Ω/hole is provided on a P-type semiconductor substrate 21 of Next, a P-type base region 25 is formed in one island region made of the N-type epitaxial layer 23 obtained in the previous step with a sheet resistance of several hundred Ω/. Next, an N+ type emitter region 26 and an N+ type collector electrode extraction region 27 are provided at several tens of Ω/hole.
02 is provided to a thickness of several hundred nm, and a portion of the insulation 82B on each region is removed to form the first opening 29.
will be established.

Next, a first metal wiring 3 made of A1 or the like with a thickness of about 1.0 μm is formed by sputtering or the like so as to cover the first opening 29.
Next, a plasma nitride film with a thickness of 1 μm is formed as an interlayer film on the entire surface (not shown). A part of the plasma nitride film, which is an interlayer film provided on the entire surface, is formed using photolithography. A plurality of N+ type emitter regions 2 are selectively removed using a technique to form second openings 33.
6. A plurality of P type base regions 25, a plurality of N+ type collectors t! The second openings 33 on the first metal arrangement 130 connected to the extraction region 7 are connected separately with second metal wiring 32 made of aluminum or the like with a thickness of about 2.0 μm to form emitters and bases.

Form each electrode of the collector.

In this embodiment, since the P-type base region 25 is provided by the first metal wiring, an extra collector region is not required, and the N-type base region 25 is
Since it can be provided as an N transistor with the minimum required area, and an insulating isolation region can be provided with the minimum size from adjacent elements, the structure is suitable for automatic mask design such as CAD.

FIGS. 2(a) and (b) are a plan view and a sectional view taken along the line B-B' of the second embodiment of the present invention, and FIG.
FIG. 2 is an equivalent circuit diagram of a horizontal PNP transistor shown in FIG.

The first aspect of the present invention up to the point where the insulating isolation region 44 is provided is as follows.
Since this is the same as the embodiment, the explanation will be omitted. By providing the insulating isolation region 44, an island region of the N-type epitaxial layer 43 is created, and in one region, a P-type emitter region 45 and a P-type collector region 46 are formed using a photolithography technique to form a sheet with a thickness of several hundred Ω/hole. Next, an N+ type base extraction region 47 is provided with a sheet resistance of several tens of Ω/hole, an insulating film 48 with a thickness of several hundred nm is provided thereon, and a portion of the insulating film 48 is removed. Then, using aluminum, the first metal wiring 50 is formed in the first opening 4.
9. Cover and set. Next, a plasma nitride film 51 with a thickness of 1.0 μm is provided as an interlayer film 51 on the entire surface, and a part of the plasma nitride film is removed using photolithography technology to form a second opening 53. Two metal interconnects &152 are formed using photolithography technology.

As shown in FIG. 2 (a), in the second embodiment,
Since the P-type emitter region 45, P-type collector region 46, and N+-type base extraction region 47 are each connected to the second metal wiring 52, it is possible to accurately maintain the transistor characteristic ratio without increasing the device exclusive area. The configuration will be as follows.

However, when wiring is formed by the conventional method, the first metal wiring 50 connected to the N+ type base extraction region 47 is provided between the emitter electrode and the collector electrode, and the effect of the present invention cannot be obtained. In the second embodiment of the invention, in particular, since the N+ type base extraction region 47, the P type collector region 46, and the P type emitter region 45 are configured as a pair, the base resistance ratio etc. can be determined with high accuracy.
The characteristic ratio of collector current to base-emitter voltage can also be achieved without increasing the area occupied by the device. In other words, when the collector current ratio is set to a ratio of 4:1 as shown in FIG. 3, the relative ratio accuracy of the collector current with an error of several percent or less is possible.

〔Effect of the invention〕

As explained above, the present invention has a plurality of emitter regions, and provides separate first metal wiring for one or more base first openings and one or more collector first openings, Since these are connected by a second metal wiring and the electrodes of each transistor are configured separately, the transistor characteristics have good match lag, excellent frequency characteristics, are suitable for automatic design such as CAD, and the area occupied by the element is small. There are effects such as being able to.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) are a plan view and a sectional view taken along the line A-A' of the first embodiment of the present invention, and FIG. 2(a). (b) is a plan view and a sectional view taken along line B-B' of the second embodiment of the present invention, and FIG. 3 is an equivalent circuit diagram of the second embodiment shown in FIGS. 2(a) and (b). Figure 4(a). An equivalent circuit diagram of the second embodiment shown in FIG. 4(a). (b) is a plan view and a sectional view taken along line cc' of an example of a conventional NPN transistor having a multiple emitter structure. 1.21.41...P-type semiconductor substrate, 2,22°42
...N+ type buried region, 3.23.43...N- type epitaxial layer, 4,24.44...Insulation isolation region, 5.25...P type base region, 6,26...・N+
type emitter region, 7, 27...N''' type collector electrode extraction area, 8, 28... insulating film, 9°29.49
...First opening, 10,30.50...First metal wiring, 13,33.53...Second opening, 12.32.
52... Second metal wiring, 51... Interlayer film, 45...
- P-type emitter region, 46...P-type collector region.

Claims (1)

[Claims] A semiconductor substrate has a plurality of emitter regions, one or more base regions, and one or more collector regions in one island region insulated and isolated on one main plane of the semiconductor substrate, and an insulating film is provided on the main plane, A plurality of first openings are provided in the insulating film in each region, a first wiring layer is provided in each of the plurality of first openings, an interlayer insulating film is provided on the first wiring layer, and the interlayer insulating film is provided in the first wiring layer. A second opening is provided in the film, and a second wiring layer is provided in which the plurality of emitter regions, the one or more base regions, and the one or more collector regions are respectively connected separately. A semiconductor integrated circuit characterized by including a transistor.