JPH01122143A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01122143A JPH01122143A JP27990987A JP27990987A JPH01122143A JP H01122143 A JPH01122143 A JP H01122143A JP 27990987 A JP27990987 A JP 27990987A JP 27990987 A JP27990987 A JP 27990987A JP H01122143 A JPH01122143 A JP H01122143A
- Authority
- JP
- Japan
- Prior art keywords
- die pad
- sealing resin
- semiconductor device
- support piece
- support pieces
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 239000011347 resin Substances 0.000 claims abstract description 18
- 229920005989 resin Polymers 0.000 claims abstract description 18
- 238000005452 bending Methods 0.000 claims abstract description 6
- 238000007789 sealing Methods 0.000 abstract description 18
- 238000005336 cracking Methods 0.000 abstract description 2
- 230000000149 penetrating effect Effects 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は樹脂封止形半導体装置に関し、特に半導体素子
が搭載されるダイパットの形状に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a resin-sealed semiconductor device, and particularly to the shape of a die pad on which a semiconductor element is mounted.
従来のこの種半導体装置は第３図に示すように構成され
ている。第３図は樹脂封止形半導体装置の側断面図で、
同図において、１はダイパット、２はこのダイパット１
上に固定された半導体素子、３は外部装置（図示せず）
に接続されるリードビンで、このリードビン３はワイヤ
４によって前記半導体素子２に接続されている。なお、
５は前記ダイパット１．半導体素子２．リードビン３の
一部およびワイヤ４を封止するための封止樹脂である。A conventional semiconductor device of this type is constructed as shown in FIG. FIG. 3 is a side sectional view of a resin-sealed semiconductor device.
In the same figure, 1 is a die pad, 2 is this die pad 1
Semiconductor element fixed on top, 3 is external device (not shown)
This lead bin 3 is connected to the semiconductor element 2 by a wire 4. In addition,
5 is the die pad 1. Semiconductor element 2. This is a sealing resin for sealing a part of the lead bin 3 and the wire 4.
このように構成された従来の半導体装置を基板（図示せ
ず）に実装するには、基板の所定のランド上またはリー
ドビン３の先端部、あるいはその両方に予め半田を供給
しておき、半導体装置を基板の所定位置に固定した後、
赤外線等で全体を加熱することによって半田を溶融させ
、半導体装置のリードビン３と基板とを接合させること
Ｋよシ行なわれていた。In order to mount a conventional semiconductor device configured in this manner on a board (not shown), solder is supplied in advance to a predetermined land on the board, to the tip of the lead bin 3, or to both, and then the semiconductor device is mounted. After fixing it in place on the board,
Traditionally, the lead bin 3 of the semiconductor device and the substrate were bonded together by heating the entire body with infrared rays or the like to melt the solder.
しかるに、このように構成された半導体装置においては
、基板等に実装する際に全体が加熱されると、ダイバン
ト１の裏面が平坦であるためダイパット１の裏面と封止
樹脂５とは強固に密着されていないから、ダイパット１
と封止樹脂５との線膨張係数の違いＫよシ第４図に示す
ように、封止樹脂５はダイパット１の裏面との密着部分
がダイパット１から剥離して膨張し、ダイパット１の側
縁部と対応する部分に応力が集中し割れてしまうという
問題があった。However, in a semiconductor device configured as described above, when the entire semiconductor device is heated when being mounted on a substrate etc., the back surface of the die pad 1 and the sealing resin 5 are firmly attached because the back surface of the die pad 1 is flat. Since it has not been done, die pad 1
As shown in FIG. 4, the part of the sealing resin 5 that is in close contact with the back surface of the die pad 1 peels off from the die pad 1 and expands, causing the side of the die pad 1 to expand. There was a problem in that stress was concentrated in the parts corresponding to the edges, resulting in cracks.
本発明に係る半導体装置は、ダイパットの一部分をダイ
パットの裏側へ折曲することによって支持片を形成し、
この支持片に貫通孔を設けたものである。In the semiconductor device according to the present invention, a support piece is formed by bending a part of the die pad to the back side of the die pad,
This support piece is provided with a through hole.
ダイパットの支持片を覆い、かつこの支持片の貫通孔内
に満たされた封止樹脂が一体に硬化することになるから
、封止樹脂は保持片によってダイパットに対して固定さ
れる。Since the sealing resin that covers the support piece of the die pad and fills the through hole of the support piece is cured together, the sealing resin is fixed to the die pad by the holding piece.
以下、その構成等を図に示す実施例によシ詳細に説明す
る。第１図は本発明に係る半導体装置を示す側断面図、
第２図は本発明に使用するダイパットを示す斜視図であ
る。これらの図において前記従来例で説明したものと同
一もしくは同等部材については同一符号を付し、ここに
おいて詳細な説明は省略する。これらの図において、符
号１１はダイパットで、このダイパット１１には、半導
体素子２が固着する側と反対側にダイパット１１の一部
分を折曲するととＫよって支持片１２が設けられておシ
、さらに、この支持片１２を貫通する貫通孔１３が穿設
されている。すなわち、このダイパット１１を形成する
には、先ずダイパット１１から平面視路コ字形のスリン
） ｌ１ｍを打抜き加工によシ打抜くことによって支持
片１２を形成する。なお、このスリン） １１ｍ打抜き
加工の際に貫通孔１３も打抜いておく。そして、前記支
持片１２をダイパット１１に対して折曲させることによ
って、このダイパット１１が形成されることになる。Hereinafter, the configuration and the like will be explained in detail with reference to the embodiment shown in the drawings. FIG. 1 is a side sectional view showing a semiconductor device according to the present invention;
FIG. 2 is a perspective view showing a die pad used in the present invention. In these figures, the same or equivalent members as those explained in the conventional example are given the same reference numerals, and detailed explanation will be omitted here. In these figures, reference numeral 11 denotes a die pad, and when a part of the die pad 11 is bent on the side opposite to the side to which the semiconductor element 2 is fixed, a supporting piece 12 is provided. A through hole 13 is bored through this support piece 12 . That is, in order to form this die pad 11, first, the supporting piece 12 is formed by punching out the support piece 11m which has a U-shape in plan view from the die pad 11. Note that the through hole 13 is also punched out during this 11 m punching process. The die pad 11 is formed by bending the support piece 12 relative to the die pad 11.
したがって、このダイパット１１を使用した樹脂封止形
半導体装置においては、支持片１２を覆い、かつこの支
持片１２の貫通孔１３内に満たされた封止樹脂５が一体
に硬化するととＫなるから、封止樹脂５は保持片１２に
よってダイパット１１に対して強固に固定されることに
なる。Therefore, in the resin-sealed semiconductor device using this die pad 11, when the sealing resin 5 that covers the support piece 12 and fills the through hole 13 of this support piece 12 is cured as a whole, K is obtained. The sealing resin 5 is firmly fixed to the die pad 11 by the holding piece 12.
以上説明したように本発明によれば、ダイパットの一部
分をダイパットの裏側へ折曲することＫよって支持片を
形成し、この支持片に貫通孔を設けたため、前記支持片
を覆い、かっこの支持片の貫通孔内に満たされた封止樹
脂が一体に硬化することになるから、封止樹脂は保持片
によってダイパットに対して強固に固定されることにな
る。したがって、半導体装置を基板等に実装する際に、
全体が加熱され封止樹脂が膨張しても、ダイパットの裏
面から封止樹脂が剥離せず、割れを防ぐことができるの
で、信頼性の高い半導体装置を得ることができる。As explained above, according to the present invention, a support piece is formed by bending a part of the die pad to the back side of the die pad, and a through hole is provided in this support piece, so that the support piece is covered and the bracket is supported. Since the sealing resin filled in the through hole of the piece is cured integrally, the sealing resin is firmly fixed to the die pad by the holding piece. Therefore, when mounting a semiconductor device on a board etc.
Even if the entire die pad is heated and the sealing resin expands, the sealing resin does not peel off from the back surface of the die pad, and cracking can be prevented, so a highly reliable semiconductor device can be obtained.
第１図は本発明に係る半導体装置を示す側断面図、第２
図は本発明に使用するダイパットを示す斜視図、第３図
は従来の樹脂封止形半導体装置を示す側断面図、第４図
は封止樹脂が膨張した状態を示す側断面図である。
２・・・・半導体素子、５・・・・封止樹脂、１１・・
・・ダイパット、１２・・・・支持片、１３・・・Φ貫
通孔。FIG. 1 is a side sectional view showing a semiconductor device according to the present invention, and FIG.
FIG. 3 is a perspective view showing a die pad used in the present invention, FIG. 3 is a side sectional view showing a conventional resin-sealed semiconductor device, and FIG. 4 is a side sectional view showing a state where the sealing resin is expanded. 2... Semiconductor element, 5... Sealing resin, 11...
...Die pad, 12...Support piece, 13...Φ through hole.
Claims (1)
てなる半導体装置において、前記ダイパットの一部分を
ダイパットの裏側へ折曲することによつて支持片を形成
し、この支持片に貫通孔を設けたことを特徴とする半導
体装置。In a semiconductor device in which a semiconductor element mounted on a die pad is sealed with resin, a support piece is formed by bending a part of the die pad to the back side of the die pad, and a through hole is provided in the support piece. A semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27990987A JPH01122143A (en) | 1987-11-05 | 1987-11-05 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27990987A JPH01122143A (en) | 1987-11-05 | 1987-11-05 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01122143A true JPH01122143A (en) | 1989-05-15 |
Family
ID=17617606
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27990987A Pending JPH01122143A (en) | 1987-11-05 | 1987-11-05 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01122143A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6812554B2 (en) | 1999-02-17 | 2004-11-02 | Renesas Technology Corp. | Semiconductor device and a method of manufacturing the same |
| US9076776B1 (en) * | 2009-11-19 | 2015-07-07 | Altera Corporation | Integrated circuit package with stand-off legs |
-
1987
- 1987-11-05 JP JP27990987A patent/JPH01122143A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6812554B2 (en) | 1999-02-17 | 2004-11-02 | Renesas Technology Corp. | Semiconductor device and a method of manufacturing the same |
| US7160760B2 (en) | 1999-02-17 | 2007-01-09 | Renesas Technology Corp. | Semiconductor device and a method of manufacturing the same |
| US7385279B2 (en) | 1999-02-17 | 2008-06-10 | Renesas Technology Corp. | Semiconductor device and a method of manufacturing the same |
| US7812464B2 (en) | 1999-02-17 | 2010-10-12 | Renesas Electronics Corporation | Semiconductor device and a method of manufacturing for high output MOSFET |
| US9076776B1 (en) * | 2009-11-19 | 2015-07-07 | Altera Corporation | Integrated circuit package with stand-off legs |
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