JPH01113354U - - Google Patents
Info
- Publication number
- JPH01113354U JPH01113354U JP1988009351U JP935188U JPH01113354U JP H01113354 U JPH01113354 U JP H01113354U JP 1988009351 U JP1988009351 U JP 1988009351U JP 935188 U JP935188 U JP 935188U JP H01113354 U JPH01113354 U JP H01113354U
- Authority
- JP
- Japan
- Prior art keywords
- container
- metal
- center
- metal column
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002184 metal Substances 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000000919 ceramic Substances 0.000 claims 1
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
Description
第1図a,bは本考案の第1の実施例の平面図
及びA―A′線断面図、第2図は本考案の第2の
実施例の断面図、第3図は従来の半導体集積回路
用パツケージの一例の断面図である。
1……容器、2……メタライズ部、3……金属
柱、4……ピン、5……台座、6……ステイツチ
部、7……ねじ穴。
Figures 1a and b are a plan view and a sectional view taken along line A-A' of the first embodiment of the present invention, Figure 2 is a sectional view of the second embodiment of the present invention, and Figure 3 is a conventional semiconductor. FIG. 1 is a cross-sectional view of an example of an integrated circuit package. 1... Container, 2... Metallized part, 3... Metal column, 4... Pin, 5... Pedestal, 6... Stitch part, 7... Screw hole.
Claims (1)
成された貫通孔に埋設された金属柱と、前記容器
底面中央部に形成された半導体チツプ固着用のメ
タライズ部と、前記容器裏面に固着され、かつ金
属柱と接続された金属製の台座とを含むことを特
徴とする半導体集積回路用パツケージ。 a ceramic container, a metal pillar embedded in a through hole formed in the center of the container, a metallized part for fixing a semiconductor chip formed in the center of the bottom of the container, and fixed to the back surface of the container, What is claimed is: 1. A package for a semiconductor integrated circuit, comprising: a metal column and a metal base connected to the metal column.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1988009351U JPH01113354U (en) | 1988-01-26 | 1988-01-26 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1988009351U JPH01113354U (en) | 1988-01-26 | 1988-01-26 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01113354U true JPH01113354U (en) | 1989-07-31 |
Family
ID=31216025
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1988009351U Pending JPH01113354U (en) | 1988-01-26 | 1988-01-26 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01113354U (en) |
-
1988
- 1988-01-26 JP JP1988009351U patent/JPH01113354U/ja active Pending