JPH01103917U - - Google Patents

Description

[Brief explanation of the drawing]

Fig. 1 is an operation/return delay circuit diagram as an embodiment of this invention, Fig. 2 is a diagram showing waveforms of main parts of the embodiment of Fig. 1, and Fig. 3 is a conventional operation/return delay circuit diagram. FIG. 4 is a circuit diagram showing waveforms of main parts of a conventional operation/return delay circuit. 1...Power supply, 2...First comparator, 3...
...Integrator circuit, 4...Second comparator.

Claims (1)

[Claims for Utility Model Registration] 1. A first comparator that outputs a pulse signal of a predetermined level based on an input signal and a predetermined threshold; connected to the output section of the first comparator;
an integrating circuit that generates a signal that rises with an arbitrary time constant in response to the rise of the pulse signal, and generates a signal that falls with an arbitrary time constant in response to the fall of the pulse signal; To the DC power supply common to the comparator,
connected to a relationship having an upper threshold and a lower threshold;
An operation/return delay circuit comprising: a second comparator that compares the output from the integrating circuit with both of the threshold values. 2 The above-mentioned utility model registration claim No. 1 has an upper limit threshold set to a value slightly lower than the potential of the common DC power supply, and a lower limit threshold set to a value slightly higher than the ground side of the common DC power supply. The operation/return delay circuit described in item 1.