JPS647430U - - Google Patents

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Publication number
JPS647430U
JPS647430U JP10065687U JP10065687U JPS647430U JP S647430 U JPS647430 U JP S647430U JP 10065687 U JP10065687 U JP 10065687U JP 10065687 U JP10065687 U JP 10065687U JP S647430 U JPS647430 U JP S647430U
Authority
JP
Japan
Prior art keywords
capacitor
resistor
power supply
reset
inverter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10065687U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10065687U priority Critical patent/JPS647430U/ja
Publication of JPS647430U publication Critical patent/JPS647430U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案のリセツト回路の一実施例を示
す回路図、第2図は従来のリセツト回路を示す回
路図である。 図面において、2はコンデンサ、3,4はイン
バータ、5は出力端子、11はツエナーダイオー
ド、12は抵抗である。
FIG. 1 is a circuit diagram showing an embodiment of the reset circuit of the present invention, and FIG. 2 is a circuit diagram showing a conventional reset circuit. In the drawing, 2 is a capacitor, 3 and 4 are inverters, 5 is an output terminal, 11 is a Zener diode, and 12 is a resistor.

Claims (1)

【実用新案登録請求の範囲】 (1) 電源からの電源電圧により充電するコンデ
ンサを備え、このコンデンサの充電中にリセツト
信号であるローレベル信号を出力するためのイン
バータとを有するリセツト回路において、前記電
源と前記コンデンサ間に接続されたツエナーダイ
オードと、前記コンデンサと並列に接続された抵
抗とを有し、前記コンデンサと前記抵抗との接続
点に前記インバータが接続されていることを特徴
とするリセツト回路。 (2) 実用新案登録請求の範囲第1項において、
前記ツエナーダイオードは、前記電源電圧が所定
の値以上に上昇したときは、予め設定された電圧
値のみを前記コンデンサおよび抵抗に印加するよ
うに設定されていることを特徴とするリセツト回
路。
[Claims for Utility Model Registration] (1) A reset circuit comprising a capacitor charged by a power supply voltage from a power supply and an inverter for outputting a low level signal as a reset signal while the capacitor is being charged, A reset device comprising a Zener diode connected between a power source and the capacitor, and a resistor connected in parallel with the capacitor, and the inverter is connected to a connection point between the capacitor and the resistor. circuit. (2) In paragraph 1 of the claims for utility model registration,
The reset circuit is characterized in that the Zener diode is set to apply only a preset voltage value to the capacitor and resistor when the power supply voltage rises above a predetermined value.
JP10065687U 1987-06-30 1987-06-30 Pending JPS647430U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10065687U JPS647430U (en) 1987-06-30 1987-06-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10065687U JPS647430U (en) 1987-06-30 1987-06-30

Publications (1)

Publication Number Publication Date
JPS647430U true JPS647430U (en) 1989-01-17

Family

ID=31328926

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10065687U Pending JPS647430U (en) 1987-06-30 1987-06-30

Country Status (1)

Country Link
JP (1) JPS647430U (en)

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