JPS61100075U - - Google Patents
Info
- Publication number
- JPS61100075U JPS61100075U JP18422884U JP18422884U JPS61100075U JP S61100075 U JPS61100075 U JP S61100075U JP 18422884 U JP18422884 U JP 18422884U JP 18422884 U JP18422884 U JP 18422884U JP S61100075 U JPS61100075 U JP S61100075U
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- signal
- diode
- transistor
- synchronous
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002131 composite material Substances 0.000 claims description 6
- 239000003990 capacitor Substances 0.000 claims description 4
- 238000000926 separation method Methods 0.000 claims description 4
- 230000001360 synchronised effect Effects 0.000 claims 4
- 238000007599 discharging Methods 0.000 claims 1
- 239000000284 extract Substances 0.000 claims 1
- 238000002955 isolation Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 8
Landscapes
- Synchronizing For Television (AREA)
Description
第１図は本考案に係る同期信号分離回路の一実
施例を示す回路図、第２図は第１図の回路に入力
される正極性複合映像信号の一例を示す波形図、
第３図は第２図のような複合映像信号を等価的に
パルス波形として簡略化して示す波形図、第４図
は第１図の回路とその前段の処理回路とをＩＣ化
した一例を示す回路図、第５図は本考案の他の実
施例を示す回路図、第６図は従来の同期信号分離
回路を示す回路図、第７図は第６図の回路に入力
される負極性複合映像信号の一例を示す波形図、
第８図は第７図の同期信号部分を拡大して示す波
形図、第９図は第７図のような複合映像信号を簡
略化して示す波形図である。
ＩＮ…複合映像信号入力端子、ＯＵＴ…同期信
号出力端子、Ｒ１１〜Ｒ１３，Ｒ２１〜Ｒ２３…
抵抗、Ｑ１１，Ｑ２１…トランジスタ、Ｉ１１，
Ｉ２１…定電流源、Ｃ１１，Ｃ２１…コンデンサ
。
FIG. 1 is a circuit diagram showing an embodiment of a synchronization signal separation circuit according to the present invention, FIG. 2 is a waveform diagram showing an example of a positive polarity composite video signal input to the circuit of FIG. 1,
Fig. 3 is a waveform diagram that equivalently shows the complex video signal shown in Fig. 2 as a simplified pulse waveform, and Fig. 4 shows an example in which the circuit shown in Fig. 1 and its preceding processing circuit are integrated into an IC. 5 is a circuit diagram showing another embodiment of the present invention, FIG. 6 is a circuit diagram showing a conventional synchronizing signal separation circuit, and FIG. 7 is a negative polarity composite input to the circuit in FIG. 6. A waveform diagram showing an example of a video signal,
FIG. 8 is a waveform diagram showing an enlarged view of the synchronizing signal portion of FIG. 7, and FIG. 9 is a waveform diagram showing a simplified composite video signal as shown in FIG. IN...Composite video signal input terminal, OUT...Synchronization signal output terminal, R11 to R13 , R21 to R23 ...
Resistor, Q 11 , Q 21 ... Transistor, I 11 ,
I21 ...constant current source, C11 , C21 ...capacitor.
Claims (1)
して充電又は放電を行うための電流供給回路と、 複合映像信号が印加される端子に第１の抵抗を
介してエミツタが接続され、前記コンデンサにベ
ースが接続され、同期信号の期間に導通してコレ
クタに接続した負荷抵抗より同期信号を取り出す
ための同期分離用トランジスタと、 このトランジスタのベース・エミツタ間に第２
の抵抗とダイオードを直列に接続して成り、前記
複合映像信号の同期信号の期間にダイオードが導
通し、前記コンデンサが放電又は充電する電流で
前記第２の抵抗に同期信号の分離レベルを決める
バイアス電圧を発生するようにしたダイオード回
路とを具備したことを特徴とする同期信号分離回
路。[Claims for Utility Model Registration] A current supply circuit for charging or discharging a capacitor whose one end is connected to a reference potential point, and an emitter connected to a terminal to which a composite video signal is applied via a first resistor. is connected, the base is connected to the capacitor, a synchronous isolation transistor conducts during the period of the synchronous signal and extracts the synchronous signal from the load resistor connected to the collector, and a second transistor is connected between the base and emitter of this transistor.
a resistor and a diode connected in series, the diode conducts during the period of the synchronization signal of the composite video signal, and the capacitor discharges or charges with a current that causes the second resistor to be biased to determine the separation level of the synchronization signal. A synchronous signal separation circuit comprising a diode circuit configured to generate a voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18422884U JPS61100075U (en) | 1984-12-06 | 1984-12-06 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18422884U JPS61100075U (en) | 1984-12-06 | 1984-12-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61100075U true JPS61100075U (en) | 1986-06-26 |
Family
ID=30741713
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18422884U Pending JPS61100075U (en) | 1984-12-06 | 1984-12-06 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61100075U (en) |
-
1984
- 1984-12-06 JP JP18422884U patent/JPS61100075U/ja active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4370569A (en) | Integratable single pulse circuit | |
| JPS6153906B2 (en) | ||
| JPS61100075U (en) | ||
| US5045943A (en) | Synchronous signal separation circuit | |
| JPH0238509Y2 (en) | ||
| JPH0134457Y2 (en) | ||
| JPS5838683Y2 (en) | Vertical blanking pulse generation circuit for television receivers | |
| JPS587725Y2 (en) | pulse delay circuit | |
| JPS5929023B2 (en) | Vertical sync separation circuit | |
| JPH028146B2 (en) | ||
| JPS6183337U (en) | ||
| SU997235A1 (en) | One-shot multivibrator | |
| SU1026287A1 (en) | Relaxation oscillator | |
| JPH0273826U (en) | ||
| JPS6025274U (en) | vertical deflection device | |
| JPS58116346U (en) | Pulse transmission circuit using photocoupler | |
| JPH0164227U (en) | ||
| JPS5850452B2 (en) | pulse shaping circuit | |
| JPS63173926U (en) | ||
| JPS6338467U (en) | ||
| JPS63111020U (en) | ||
| JPH0348925U (en) | ||
| JPS58166146U (en) | Pulse transmission circuit using photocoupler | |
| JPH06268889A (en) | Synchronizing signal separator | |
| JPS62105628U (en) |