JP7784766B2 - 積層構造体、電子デバイス、電子機器及びシステム - Google Patents

積層構造体、電子デバイス、電子機器及びシステム

Info

Publication number
JP7784766B2
JP7784766B2 JP2024544592A JP2024544592A JP7784766B2 JP 7784766 B2 JP7784766 B2 JP 7784766B2 JP 2024544592 A JP2024544592 A JP 2024544592A JP 2024544592 A JP2024544592 A JP 2024544592A JP 7784766 B2 JP7784766 B2 JP 7784766B2
Authority
JP
Japan
Prior art keywords
film
crystal
substrate
laminated structure
crystalline
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2024544592A
Other languages
English (en)
Japanese (ja)
Other versions
JPWO2024048764A1 (https=
JPWO2024048764A5 (https=
Inventor
健 木島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Gaianixx Inc
Original Assignee
Gaianixx Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gaianixx Inc filed Critical Gaianixx Inc
Publication of JPWO2024048764A1 publication Critical patent/JPWO2024048764A1/ja
Publication of JPWO2024048764A5 publication Critical patent/JPWO2024048764A5/ja
Application granted granted Critical
Publication of JP7784766B2 publication Critical patent/JP7784766B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/08—Oxides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/81—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/07—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
    • H10N30/074—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by depositing piezoelectric or electrostrictive layers, e.g. aerosol or screen printing
    • H10N30/076—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by depositing piezoelectric or electrostrictive layers, e.g. aerosol or screen printing by vapour phase deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/07—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
    • H10N30/074—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by depositing piezoelectric or electrostrictive layers, e.g. aerosol or screen printing
    • H10N30/079—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by depositing piezoelectric or electrostrictive layers, e.g. aerosol or screen printing using intermediate layers, e.g. for growth control
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/80—Constructional details
    • H10N30/85—Piezoelectric or electrostrictive active materials
    • H10N30/853—Ceramic compositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/80—Constructional details
    • H10N30/88—Mounts; Supports; Enclosures; Casings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Recrystallisation Techniques (AREA)
JP2024544592A 2022-08-31 2023-08-31 積層構造体、電子デバイス、電子機器及びシステム Active JP7784766B2 (ja)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
JP2022138850 2022-08-31
JP2022138851 2022-08-31
JP2022138852 2022-08-31
JP2022138852 2022-08-31
JP2022138851 2022-08-31
JP2022138850 2022-08-31
PCT/JP2023/032023 WO2024048764A1 (ja) 2022-08-31 2023-08-31 結晶、積層構造体、素子、電子デバイス、電子機器及びシステム

Publications (3)

Publication Number Publication Date
JPWO2024048764A1 JPWO2024048764A1 (https=) 2024-03-07
JPWO2024048764A5 JPWO2024048764A5 (https=) 2025-04-17
JP7784766B2 true JP7784766B2 (ja) 2025-12-12

Family

ID=90097982

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2024544592A Active JP7784766B2 (ja) 2022-08-31 2023-08-31 積層構造体、電子デバイス、電子機器及びシステム

Country Status (2)

Country Link
JP (1) JP7784766B2 (https=)
WO (1) WO2024048764A1 (https=)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001257344A (ja) 2000-03-10 2001-09-21 Toshiba Corp 半導体装置及び半導体装置の製造方法
JP2002314067A (ja) 2001-04-13 2002-10-25 Toshiba Corp 半導体装置およびｍｉｓ型電界効果トランジスタの製造方法
WO2005038929A1 (ja) 2003-10-15 2005-04-28 Nec Corporation 半導体装置の製造方法
JP2007019515A (ja) 2005-07-07 2007-01-25 Infineon Technologies Ag 半導体装置、半導体装置の製造方法およびトランジスタ装置の操作方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023145808A1 (ja) * 2022-01-27 2023-08-03 株式会社Gaianixx 結晶、積層構造体、電子デバイス、電子機器及びこれらの製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001257344A (ja) 2000-03-10 2001-09-21 Toshiba Corp 半導体装置及び半導体装置の製造方法
JP2002314067A (ja) 2001-04-13 2002-10-25 Toshiba Corp 半導体装置およびｍｉｓ型電界効果トランジスタの製造方法
WO2005038929A1 (ja) 2003-10-15 2005-04-28 Nec Corporation 半導体装置の製造方法
JP2007019515A (ja) 2005-07-07 2007-01-25 Infineon Technologies Ag 半導体装置、半導体装置の製造方法およびトランジスタ装置の操作方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
TAHIR Dahlang, OH Kun Suhk, KANG Jae Hee, TOUGAARD Sven，COMPOSITION DEPENDENCE OF DIELECTRIC AND OPTICAL PROPERTIES OF Hf-Zr-SILICATE THIN FILMS GROWN ON Si，THIN SOLID FILMS，2016年09月05日，616，425 - 430

Also Published As

Publication number Publication date
JPWO2024048764A1 (https=) 2024-03-07
WO2024048764A1 (ja) 2024-03-07

Similar Documents

Publication Publication Date Title
US6709776B2 (en) Multilayer thin film and its fabrication process as well as electron device
US6432546B1 (en) Microelectronic piezoelectric structure and method of forming the same
US20020006733A1 (en) Multilayer thin film and its fabrication process as well as electron device
CN1692506A (zh) 薄膜叠层体、采用该薄膜叠层体的电子装置、及调节器以及调节器的制造方法
US20040217444A1 (en) Method and apparatus utilizing monocrystalline insulator
CN1320603C (zh) 在绝缘体上的外延半导体结构和器件
JP2001077112A (ja) 積層体，積層体の製造方法及び半導体素子
JP7784766B2 (ja) 積層構造体、電子デバイス、電子機器及びシステム
JP7751916B2 (ja) 積層構造体、電子デバイス、電子機器及びシステム
TW202443887A (zh) 積層構造體、元件、電子器件、電子機器及系統
CN1449458A (zh) 薄膜金属氧化物结构及其制造方法
US11233129B2 (en) Semiconductor apparatus
US20040248422A1 (en) Fabrication method of polycrystalline silicon TFT
JP7784720B2 (ja) 積層構造体、電子デバイス、電子機器及びシステム
JP2005268662A (ja) ３次元デバイスの製造方法
US6482538B2 (en) Microelectronic piezoelectric structure and method of forming the same
TW202423844A (zh) 結晶、積層構造體、元件、電子器件、電子機器及系統
TW202424232A (zh) 結晶、積層構造體、元件、電子器件、電子機器及系統
KR100738852B1 (ko) 반도체 메모리 소자 및 초음파 센서
JP4115789B2 (ja) 半導体装置の製造方法
JP2023134332A (ja) 積層構造体、半導体装置及びこれらの製造方法
JP2002083937A (ja) 強誘電体膜、半導体装置及びこれらの製造方法
JPH0722315A (ja) 半導体膜の製造方法
CN115867121B (zh) 一种柔性神经视网膜器件及其制备方法
EP4611500A1 (en) Ferroelectric device and method

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20250203

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20250203

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20250314

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20250430

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20250612

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20250624

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20250909

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20251027

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20251104

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20251125

R150 Certificate of patent or registration of utility model

Ref document number: 7784766

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150